Other Parts Discussed in Thread: USB2ANY
Dear TI,
From the PLL LF Support tab inside TICS Pro, we have
please provide a recommendation for the following PLL settings:
PLL1 Bandwidth: Hz
PLL1 Reference Frequency: 100MHz
VCXO Frequency: 100MHz
VCXO Gain: kHz/V
PLL2 Bandwidth: kHz
PLL2 Reference Frequency: 200MHz
PLL2 VCO Frequency: 6GHz
I think I’ve configured the LMK04610 for a pair of 200MHz outputs, and six 100MHz outputs. I do want some of the outputs configured for HSDS and a couple configured for HCSL. The PLL1 reference frequency and the VCXO frequency are 100MHz as shown above. The PLL2 reference frequency is 200MHz because of the doubler. The PLL2 VCO frequency is 6GHz as shown above.
I haven't entered anything above for the PLL1 or PLL2 bandwidths or the VCXO gain. I'm not sure what the bandwidths should be; I want low jitter clocks. I'm not sure what the VCXO Gain is. The data sheet (attached) for the Connor-Winfield VCXO (TB522-100.0M) provides two gains for two options in units of ppm/V: 8.00 (options 4 and 5) and 4.50 (option 9). The VCXO gain is positive, so PLL1_DIR_POS_GAIN should be 0?
What else must be defined in the configuration file (attached)? PLL1 and PLL2 loop filter parameters? Lock detect parameters? How much of this am I supposed to figure out? Anything obviously wrong with the configuration file?
Thanks, Jeff