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LMK04816BEVAL: Problem deriving 125 MHz after changing VCXO

Part Number: LMK04816BEVAL
Other Parts Discussed in Thread: CODELOADER

I am trying to configure a LMK04816B Eval board  device using TICs Pro.  I am trying to generate 125 and 6.256 MHz clocks on the device. I have swapped out the 122.88 MHz VCXO (U2) with a 100 MHz version and I am driving CLKIn1 with 100 MHz (0.0 dBm).   

I performed the following in TICS Pro and my Eval board:
- Load the default 122.88 MHz ClkIn1, 122.88 MHz VCXO
- Change the reference values on the PLL1 and PLL2 pages to 100 MHz
- Turn off EN_SYNC
- Modify the LD and HOLD Status pins to gather the following results:

PLL1_R/2 = 416.7 kHz
PLL1_N/2 = 416.7 kHz
PLL1 LD Locked

PLL2_R/2  = ~50 MHz
PLL2_N/2  = 56 MHz
PLL2 LD  = Not Locked

(I noticed that the PLL2 VCO output was 2 GHz which TICs indicated was out of range for the PLL.  I changed N Divider to 12 to place VCO at 2400 MHz)
PLL2_R/2  ~50 MHz
PLL2_N/2  47 MHz
PLL2 LD  Not Locked

What do I need to do to lock the PLL2 at a frequency that derive 125 MHz and 6.25 MHz?  Are there any other modifications that I need to do beside swap out the VCXO?

Thanks,

Doug

  • FWIW:  The output from the VCXO looks like it is a clean 100 MHz.

  • Hi Doug,

    Can you check the voltage at the VTUNE2 test point? It sounds like the VCO is being forced to the rail. Maybe the VCO polarity was flipped or there is a wire-off somewhere in the loop filter.

    Are you using any of the 0-delay settings? 0-delay can cause TICS Pro to misreport the actual VCO frequency, see the user's guide section "Programming 0-Delay Mode in CodeLoader" for more information.

    Regards,

  • I am using the default Dual PLL functionality.   I am trying to make as few changes as I can from the default of the device. 

    I measured 3.26 V on the Vtune2 test point which certainly does seem like it's at the rail. 

    Other than swapping out the VCXO, I don't see any other changes to the board which had previously worked at 122.88 MHz.

    Doug

  • Using the Monkeys reproduce Shakespeare method of troubleshooting, I reduced the PLL2 phase detector frequency from 100 MHz to 50 MHz (along with the appropriate doubling of the N Divider) and my VTune2 TP stabilized and PLL2 locked. 

    I'm not sure what the impact of doing this truly is, but the device now appears to work as desired. 

    Any input on why halving the phase detector frequency stabilized my PLL2?