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Part Number: CDCE72010EVM
Hi,
I've spent a few weeks trying to solve this, hopefully someone here can help:
I have a CDC72010 Evaluation board with a 622.08MHz VCXO (located off the EVM board, connected using the VCXO_IN SMAs, datasheet: http://www.conwin.com/datasheets/vx/vx605.pdf). The VCXO is powered using the VCC_CP supply from the EVM, and VCTRL is taken from JP11-NP on the EVM. I've disconnected power from the 491.52MHz VCO on the EVM by removing L9 inductor.
My reference is a 10MHz OCXO. Dividers are set to FB=36, N=216, M=125 to achieve 80kHz PFD.
I can read the M and N divider outputs from the status pin, for both REF_CLK and FB an 80kHz waveform is there, so I suspect inputs are fine.
I'm using loop filter 4 on the EVM. My output wanders to a higher frequency and I do not see any indication of it trying to pull down to the expected 622.08MHz.
[REGISTERS]
REG0=E83C0270
REG1=E9020031
REG2=68000002
REG3=E9800003
REG4=68000104
REG5=40001505
REG6=EB400006
REG7=68000327
REG8=68000018
REG9=69840C09
REG10=035C07CA
REG11=98002B0B
REG12=60409B0C
[EVM_OUTPUTS]
PWR_EN=0
DEV_COMM_LED=1
PLL_LOCK_LED=0
CD_MODE_LED=0
Y0_TERM=1
Y1_TERM=1
Y2_TERM=1
Y3_TERM=1
Y4_TERM=1
Y5_TERM=1
Y6_TERM=1
Y7_TERM=1
Y8_TERM=1
Y9_TERM=1
MODE_SEL=1
REF_SEL=1
AUX_SEL=1
RESET=0
POWER_DOWN=0
Hi Aaron,
I am currently looking into this for you to help. Please give me a few days. I'll provide a followup with what I've learned.
In the meantime, it looks like your PLL isn't locking. The PLL_LOCK_LED=0 as well as the wander seem to indicate this.
Are you using the board with Digital or Analog lock detect, as chosen by the JP_3_12 jumper?
Regards,
Adam
Hi Adam,
Yes, I have the JP_3_12 jumper connected to the 2 pins closest to C59.
Since writing this I've also tried using the EVM supplied 491.52MHz VCO, just to be sure everything is setup correctly and start from a working config. With an external 10MHz OCXO I still don't get a lock.
The largest PFD I can get with those clocks is 80kHz, so I'm using Loop Filter 4, CP=3ma, FB=64, N=96, M=125. As before with this configuration I can see the 80kHz PFD inputs from both the feedback path and the ref clock path (using the status pin). This has me perplexed, I expected the default board to work with these clocks.This is the config using the onboard VCO:
[REGISTERS]
REG0=003C0270
REG1=00020001
REG2=00000002
REG3=00000003
REG4=00000104
REG5=00001505
REG6=E9400006
REG7=00000017
REG8=000000D8
REG9=69040089
REG10=017C07CA
REG11=98003D0B
REG12=6040BB0C
[EVM_OUTPUTS]
PWR_EN=1
DEV_COMM_LED=1
PLL_LOCK_LED=0
CD_MODE_LED=0
Y0_TERM=1
Y1_TERM=1
Y2_TERM=1
Y3_TERM=1
Y4_TERM=1
Y5_TERM=1
Y6_TERM=1
Y7_TERM=1
Y8_TERM=1
Y9_TERM=1
MODE_SEL=1
REF_SEL=1
AUX_SEL=1
RESET=0
POWER_DOWN=0
These settings do not fit my needs, but I did expect them to work on the factory board.
Hi Aaron,
It's interesting that you're having trouble getting it to work even with the default board. Could you please confirm what version of the software you're running as well as your operating system?
Thanks,
Adam
Hi Adam,
I'm running Windows 10, I've used both 1.2.8 and 1.3.0 versions of the software. Both versions appear to function properly based on measured device outputs when changing registers. v1.3.0 occasionally reports an error and closes so most of my work has been with 1.2.8.
Can you share a default ini file for the eval board? I've looked everything over but perhaps I missed a bit somewhere.
Thanks for the support
Aaron
Hi Aaron,
Unfortunately I am not able to provide the .ini file to you. Have you had any luck since we last spoke?
Adam