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CDCLVP111-SP: LVCMOS input specs

Mark Guastaferro
Genius 11185 points
Part Number: CDCLVP111-SP
Other Parts Discussed in Thread: CDCLVP1204

Using the CDCLVP111-SP clock buffer with a 3.3V LVCMOS single-ended input, following interface described in Figure 8 of the data sheet. It works fine, but there is a concern that the clock input signal levels do not meet the spec requirements listed in section 6.6 for Vcc = 3.3V, VEE = 0V, Particularly Vid. 

Also, not sure what Vih/Vil specs refer to as they call out CLK_SEL which should be LVTTL/LVCMOS compatible. For example with Vcc = 3.3V, Vih limits are 2.135V min, 2.42V max.  Does this mean CLK_SEL level needs to be between these values, or that this is the min and max of the threshold voltage? 

Does this mean the Clock needs to be attenuated? I noticed that some CDCLVP clock buffers (like CDCLVP1204) had separate specs for LCMOS input as a single-ended input.   

Input frequency is 60 MHz in this application

  • 0
    TI__Genius 16845 points

    Hi Mark,

    CDCLVP111-SP datasheet does not indicate the parameters for a single-ended input, but single-ended signaling is generally at slower rates than differential. If you would like to reduce the swing to meet the VID given in the datasheet, load the LVCMOS clock line with 50ohm at the CDCLVP111-SP input to reduce the swing (and VID) by half.

    It appears that these VIH and VIL calues are for the CLK_SEL pin. I design around the max value for VIH and min value for VIL.

    Kind regards,
    Lane

  • 0 in reply to Lane Boyd
    TI__Genius 11185 points

    Hi Lane,

    Thanks for the comments.  The 50 ohm load on the CLK input might be a good idea as this is for a space project and we want to make sure the the device is operated within optimal bounds. With no direct LVCMOS, the LVPECL VID spec looks to be the best guidance. 

    Your suggestion on the VIH/VIL limits is what I was thinking as well.  

  • 0 in reply to Mark Guastaferro
    TI__Genius 16845 points

    Hi Mark,

    One way to apply the 50ohm load is using a resistor divider with 100ohms on the top and bottom, to VCC and GND respectively. That will provide a 50ohm bias to VCC/2, which is within the acceptable common mode range. Remember to also bias the complementary input to VCC/2 when using a single-ended input

    Kind regards,
    Lane