CDCEL913: LVCMOS Crystal input and the solution of phase sync

Hello Kazuki,

If you want to be able to have a 3.3 V LVCMOS output, you must use the CDCE913 device. The CDCEL913 only permits an output supply voltage up to 1.9 V as shown below.

The CDCEL913 has an output skew with a maximum of 50 ps as shown below. Although this is a low value, it can not be assumed that the output phases are completely synced. For most applications, this is an acceptable difference in phase between outputs.

The CDCEL913 does not have complete phase sync between the input and the output. 

The LMK1C1103 would be a much better device for your purposes. The output skew still has a maximum of 50 ps, but the additive jitter is 20 fs. Additive jitter is the time domain version of phase variation between input and output.

Regards,

Kia Rahbar

Hello Kia,

Thank you for your explanation.

I'm little confusing.
In previous thread you explained Y1 and Y2's phase is not synced as following.
"First, if you want to provide a 72 MHz input, make sure that the LVCMOS input mode is selected. Second, Y1 and Y2 will not be phase synchronized because the output division to make Y2 = 12 MHz changes the phase from that of Y1 = 72 MHz. "
However, you said  Y1 and Y2 is synced as far as my understanding.
Would you tell me which is correct ?

Also, sorry for making you confusion.
I'd like to know about whether this device can support 3.3V LVCMOS output VCXO for clock input under LVCMOS input mode.
I don't discussing about output logic level.
Would you answer it?


Best regards,
Kazuki Kuramochi

Hello Kazuki,

Depending on your requirements for output skew (phase sync) the CDCEL913 output skew of 50 ps can be sufficient to claim phase sync is achieved. For most applications, an output skew of 50 ps is acceptable. If you provide me your requirements I can provide you a definite answer. The wording in my first post was unclear. Please follow my responses in this post.

I am still unclear what you are asking in the second question. What do you mean by "LVCMOS output VCXO"? The outputs are all only LVCMOS.

Regards,

Kia Rahbar

Hello Kia,

As for output phase, I understood that this device's outputs are synced within 50ps however we cannot distinguish whether end application can regard clock is synced.

In regard to input signal, I think VCXO input mode is focusing on receiving differential clock signal from VCXO.
However, There is VCXO which have LVCMOS output as like as this.
Then, I'd like to know about whether we can use LVCMOS input mode for such as VCXO which have LVCMOS output.

Best regards,
Kazuki Kuramochi

Hello Kia,

Would you explain why we must need to use VCXO?
Input signal type is same. So I think we can use LVCMOS output VCXO with CDCEL913 if we don't use Vctrl pin.
Also, VXSG-Y6S7 is just example. We are focusing on not only this device but also all of LVCMOS output type VCXO.

Best regards,
Kazuki Kuramochi

Kia-san,

Sorry for my late reply.
My understanding is that we can use VCXO with LVCMOS mode when we don't use Vctrl and output type is LVCMOS.
In other word,  We can use VCXO for LVCMOS as far as we treat VCXO as just LVCMOS output type crystal.

Is this right?


Best regards,
Kazuki Kuramochi

Kia-san,

Sorry for making your confusion.

I want to know whether we can use LVCMOS mode with VCXO if we don't use Vctrl.
I think I can use it as far as I treat VCXO as LVCMOS clock source if I don't use Vctrl.

Is it possible?


Best regards,
Kazuki Kuramochi

Hello Kia,

I don't think to switch between LVCMOS and VCXO mode.
I just want to use CDCEL913 under LVCMOS input mode.
Then I just want to know whether we can use LVCMOS output type VCXO for clock source of CDSEL913 if we don't need to use CDCEL913's Vctrl(In other word, We don't need to frequency control for VCXO from CDCEL913 and we just treat LVCMOS output type VCXO as clock generator).

Best regards,
Kazuki Kuramochi