CDCE913-Q1: Propagation delay when PLL is used

Yuta Kurimoto

Expert 8290 points

Part Number: CDCE913-Q1

Hello Team,

I got some questions from customer about the CDCE913-Q1.

Q. How much propagation delay from VDD(1.8V) ramp up to start output clock?

Q. How much propagation delay from VDD(1.8V) ramp down to stop output clock?

[Condition]

VDD = 0V~1.8V, VDDOUT=3.3V, PLL is used.(NOT bypassed)

Input clock = 27MHz, Output clock =27MHz, 74.1774MHz

Thanks,

Yuta Kurimoto

over 3 years ago

0 Amin Eshraghi over 3 years ago

TI__Expert 6140 points

Hello,

This is covered in section: 11.2.2.3. The startup time is dominated by the crystal (~250 us) which is an order of magnitude larger than the PLL lock time (~10 us). So that would bring it to about ~260 us.

Thanks and regards,

Amin

Clock & timing

Clock & timing forum

CDCE913-Q1: Propagation delay when PLL is used