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LMK5B12204: Clock gernerator sync to a GPS 1PPS clock.

Yonghui zhu
Intellectual 430 points
Part Number: LMK5B12204
Other Parts Discussed in Thread: LMK05318B, LMK05028

Hi Expert, 

We want to use LMK5B12204 to generate a high frequency clock (10M, 40M, etc), and the rising edge needs to be aligned to a GPS 1PPS clock.  So all separated systems with a GPS 1PPS clcok can get accurae phase-align clock. Can this chip get  this goal?

Another question is, what's the fequency/temperature chracterritic of this chip? Can we use it to replace a TCXO crystal oscillator? 

Thanks

Peter

  • 0
    TI__Expert 6140 points

    Hi Peter, 

    So intention is to use 1 pps as the reference input to this device and have the output (which is 10 MHz, 40 MHz, etc) phase aligned with the input (every 10 million cycles)? 

    I think that implies a zero delay mode - which LMK5B12204 isn't ideal for - but I'll wait for you to confirm. 

    Temperature grade is -40C - 85C. 

    Frequency wise once the DPLL is locked - the outputs will be at 0 ppm from the reference input source. So you it will require an XO to lock the APLL (this can be 50 ppm) and a reference input to lock the DPLL. The output frequency error will be dependent on the reference input. However DCO mode (Digital control oscillator) will allow ppb - ppm correction of the reference source in order to achieve ideal frequency. 

    Thanks and regards,

    Amin 

  • 0 in reply to Amin Eshraghi
    Intellectual 430 points

    Hello Amin, 

    Yes, I want all outputs are phase aligned with this 1PPS (from GPS module) every 10 Million cycle.  Do you mean outputs from one part is ok, but not ok for all outputs if there are multiple parts because of its underminded delay?  If so, which TI part is suitalbe for such application? 

    Thanks

    Peter 

  • 0 in reply to Yonghui zhu
    TI__Expert 6140 points

    Hi Peter, 

    Yes, so this feature on our devices would be called zero delay mode - making the output aligned with the input. Unfortunately, this isn't absolute zero - this just implies deterministic delay from the input to output. So in that sense it doesn't provide what you need - absolute alignment. 

    Furthermore, LMK5B12204 does not have this feature. 

    LMK05318B does support this on OUT_7 only, but zero delay mode has an error of +/-1 VCO clock. Statistical probability (pretty evenly distributed) on whether it'll come up with +1 VCO clock, -1VCO clock, or "aligned" with VCO clock - which again just implies a deterministic offset. 

    LMK05028 supports zero delay mode on all outputs and does not have error. However, it is not not absolute zero - there's inherent offset between the input and output once zero delay mode is achieved. This is specified on the datasheet with a typical value of 2 ns. 

    Thanks and regards,

    Amin 

  • 0 in reply to Amin Eshraghi
    Intellectual 430 points

    Hi Amin, 

    Thanks for clarification. It seems LMK05028 is more suitable. Could you help to check ADI part AD9544? It has zero delay feature.  We want to use the best solution. We have had enough TI parts on boards now:)

    www.analog.com/.../ad9544.html

    Thanks

    Peter

  • 0 in reply to Yonghui zhu
    TI__Expert 6140 points

    Hi Peter, 

    LMK05028 is probably  a solid solution. AD9544 does have more outputs (10 vs 8) and power consumption is lower but jitter is similar to 5028. It would fully depend on the configuration that's needed. 

    Thanks and regards,

    Amin 

  • 0 in reply to Amin Eshraghi
    Intellectual 430 points

    Hi Amin, 

    I will consider LMK05208. To achieve 40MHz phase-aligned output, there will be 2 inputs

    1. A 1PPS form GPS module

    2. A 40MHz clock from a TCXO lscillator, https://www5.epsondevice.com/en/products/tcxo/tg7050skn.html

    The 1PPS will be connected to IN0 pin, and the 40MHz clock will be connected to TCXO_IN pin, and leave XO pin unconnected. A phase-aligned 40MHz will be available from OUT4/5 pins if OUT4/5 is selected for zero delay.  Is such connection correct? 

    By the way, if OUT4/5 is selected for zero delay source,  does it mean OUT6 and OUT7 are not aligned with OUT4/5 even they are configured with same frequency? If so, OUT6 and OUT7 can not be our phase-aligned output source, right?

    Thanks

    Peter

  • 0 in reply to Yonghui zhu
    TI__Expert 6140 points

    Hi Peter,

    XO connection is absolutely necessary. Without the APLL will not lock. 

    TCXO input is used for TCXO DPLL in 3 loop mode - which I don't think you need. You can still use the TCXO for the XO input. 

    Yes, in zero delay mode, the selected outputs will provide a deterministic delay from the input to the output once DPLL is locked. 

    With regards to other outputs not selected in zero delay - I believe you're correct. We can sync the outputs normally - which would be mean the outputs come up together as soon as they're up (when APLL locks). However because zero delay updates the phase of the selected outputs to a specific position with reference to the input - I believe at that point you lose alignment with the the other channels. I will double check this. 

    Thanks and regards,

    Amin