Other Parts Discussed in Thread: CDCE6214-Q1, LMK05318B
I have questions for CDCE(L)949.
Fisrt, I'd like to know about each output which is generated by same PLL are synchronized output phase.
We'd like to generate 48kHz and 3.072MHz clock.
Also We need to synchronize 48kHz clock rising edge and 3.072MHz clock.
Is this device can achieve this phenomena?
Second, Could you provide specification variation regarding output jitter and power consumption?
We need following performance and it can achieve this as room temp.
・Cycle to cycle/ Period jitter = lower than 290ps
・Power consumption = Lower than 20mA when device is enabled
Then, would you tell me whether this device can meet this specification under recommended operating condition?
If CDCE(L)949 cannot satisfy this requirement, would you provide other appropriate device?