Hi,
Is there any frequency limitation when feeding a single ended input clock to CLKin0 or CLKin1 pin more constraining than the "0.001 to 3100 MHz" frequency range (considering CLKin_MUX= DivideCLKinX_DIV= 2 to 8)?
Thank you,
JY
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
Is there any frequency limitation when feeding a single ended input clock to CLKin0 or CLKin1 pin more constraining than the "0.001 to 3100 MHz" frequency range (considering CLKin_MUX= DivideCLKinX_DIV= 2 to 8)?
Thank you,
JY
Hi JY,
Single ended wouldn't have an extra frequency range limitation.
73,
Timothy