Can you provide a simple model of the LVDS output stage for the CLK/SCLK outputs? I want to see how the output levels and common mode voltage are affected by terminating the output with a thevenin termination as we do on some of our ADC interfaces.
I made a simple TINA model based on how I assume the LVDS output is driven (current steering H-bridge with a Vcm loop), but the results don't align with actual board measurements.