Other Parts Discussed in Thread: DAC39J84, , DAC37J82, DAC37J84
Hi,
We are planning to use DAC39J82 in our application where the following are our requirements (in both cases DAC LO is not used)
- For Output 1: FDAC is around 2800 MSPS, FDATA is around 1400 MSPS, interpolation factor 2x; the useful spectrum of the signal falls from 0 Hz to around 460 MHz
- For Output 2: FDAC is around 1000 MSPS, FDATA is around 500/250 MSPS, interpolation factor 2x/4x; the useful spectrum of the signal falls from 0 Hz to around 85 MHz
With regard to this we have few queries as mentioned below:
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Is it possible to implement both the outputs mentioned above using a single DAC39J82, assuming the ACLR (Interchannel leakage/coupling) is within the limits? If possible what are the steps and sequences for configuration?
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From the Baseband processor to the DAC, Real data samples shall be sent or IQ data samples shall be sent?
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If IQ data needs to be sent
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For Output 1 generation, the JESD Line rate will be 7 Gbps; LMF = 821, is this a Valid JESD configuration, or are we missing anything here?
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As per "Table 9. JESD204B Frame Assembly Byte Representation" in the datasheet, for LMF = 821, Sample positions are given with 3 columns from I0Q0 to I5Q5, shouldn't there be another column indicating the Sample and octets positions(I6Q6 and I7Q7) across Line no 0 to 7? Or is the Diagram/Table correct?
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Suppose both the channels of the DAC operate @ 2800 MSPS (2x interpolation), is it possible to meet the Data throughput requirements using JESD( as the calculated line rate is 14 Gbps)? Is it a valid configuration or is there a constraint on Max FDAC/FDATA if we want to use Both the Channels of the DAC (because JESD throughput is the bottleneck here)? What is the configuration of JESD LMF if Both the channels are used?
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JESD Parameter M: As per our knowledge, if it's Complex IQ data and one Channel is used then M = 2 corresponds to two Complex convertors; suppose two channels are used with complex IQ data then M = 4, is this convention correct wrt DAC39J82?
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If Real data needs to be sent
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What the conditions/limitations wrt using Interpolation, Mixers, clock, etc?
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If FDAC = 2800 MSPS with 2x interpolation, then as per "6.7 AC Electrical Characteristics" then the internal DAC PLL cannot generate this frequency, so do we need to use DACCLKP/N to directly drive the 2800 MHz clock? If Yes, "6.6 Digital Electrical Characteristics" says the Max limit for DACCLKP/N is 2.5 GHz, are there any Errors in the Datasheet wrt this value? Or is there a limitation/conditions on operating @ 2800 MSPS as well?
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In Addition to the previous question, if we use FDAC = 2700 MSPS with 2x interpolation, can the internal DAC PLL generate this clock frequency? As per 6.7, it should be able to, but are there any conditions/limitations here? Also any conditions on the Min and Max frequency limits of DACCLKP/N in order to drive DAC PLL?
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If we use Xilinx Based JESD IP or any third-party-based standard JESD IPs would this affect the functioning of the DAC? Are there any strict rules on the JESD interface wrt DAC39J82?
Please provide you valuable inputs which would really help us to proceed further.
FYI, using the following datasheet which we got from the TI website: SLASE47 –JANUARY 2015
Thanks,
Kiran