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ADS1282-SP: Power-on Reset, Pin Reset, SPI reset

Daniele Lippi
Prodigy 150 points
Part Number: ADS1282-SP
Other Parts Discussed in Thread: ADS1282

Dear all,

I have some question about Power-ON Reset and HW reset.

1. Datasheet reports that at power-up, ADC removes internal reset after Trst = 2^16/Fclock, then first data is output after Tdr = 63/Fdata.
Since ADC starts in FIR Mode with Fdata = 1000SPS and my Fclock = 4MHz, Trst =~16ms and Tdr =~ 64ms.

2. Datasheet reports that Tdr = 63/Fdata after hardware reset by nRESET pin cycling.

My questions are:

  1. Is, in case 1, possible to do any operation, including synchronizing, configure or calibrate the ADC just after Trst without waiting for first nDRDY negative edge (i.e. Tdr)?

  2. Is, in case 2, possible to do any operation, including synchronizing, configure or calibrate the ADC just after Trst without waiting for first nDRDY negative edge (i.e. Tdr)?

  3. Does the ADC starts converting just after either power on reset or pin reset removal and consequently be possible to retrieve converted data upon the first occurring  nDRDY negative edge?

  4. Does power-on reset or pin reset require SPI reset before sending commands to the ADC or retrieving conversion data?
    Datasheet says SPI is reset by holding SCLK low for 64 nDRDY periods. Does it means Tspi_rst = 64/Fdata? (after reset removal it would be 64ms).

I'll thank you in advance.

Daniele

 

 

  • 0
    TI__Mastermind 44610 points

    Hi Daniele,

    1. Yes, you can communicate with the device as soon as the internal reset is released. However, since there is no visual indication of when this occurs I'd recommend adding some delay margin to ensure that the supplies have settled and the 2^16/fCLK timer has expired. You might also want to readback a known non-zero or non-"FF" register value during start-up to check if the returned value is what you expect, that will provide an indication that the device is active and ready to communicate.

    2. After a hardware reset or SPI command reset, I would wait at least 4/fCLK periods before issuing another command since it usually it takes one or two clock cycles for the device to complete the reset. If you are not removing power to AVDD, AVSS, or DVDD then you do not need to wait for tRST (i.e. 2^16/fCLK).

    3. The device will automatically start converting after the internal reset is released during power-on, after resetting the device, or after coming out of standby mode. Whenever the device starts or restarts from synchronization the first conversion always takes longer because the digital filter must complete multiple (internal) conversions to allow for the digital filter to settle (e.g. data must propagate to all the digital filter taps before a stable result is available). The ADS1282 "masks" these internal conversions by holding /DRDY high until the digital filter has settled, but the first /DRDY falling edge indicate that settled data is available.

      The only exceptions to this would be...
      a) If the digital filter has previously settled and a large step change occurs on the input during the conversion process. In this case, unless you issue a SYNC command to reset the digital filter and restart conversions, the ADS1282 will continue to provide conversion results at expected data rate and you can then observe the intermediate conversion results as the filter settles.
      b) In continuous sync-mode, if the ADS1282 re-synchronizes due to the SYNC clock being out of phase with fCLK, then /DRDY will continue to pulse at the expected data rate, but you will read all ZEROS until the filter settles (this is done to keep data samples aligned in time in cases where multiple ADS1282's are synchronously sampling and re-synchronizing independently).

    4. See my response to your other E2E question here: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1071347/ads1282-sp-power-on-sequence. Resetting the SPI interface should only be needed if the SCLK signal was allowed to float (such as during power up if your controller is also powering up at the same time as the ADS1282).

    Please let me know if you have any remaining questions.

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Prodigy 150 points

    Hi Christopher,

    now I have another question:

    Can ADC_CLOCK go on running during AVDD/AVSS power cycling without causing unexpected / undesired behavior after ADC is repowered with analog power supply?

    Best regards,

    Daniele

  • +1 in reply to Daniele Lippi
    TI__Mastermind 44610 points

    Hi Daniele,

    I believe so...most likely the clock signal will be internally gated while the device is held in internal reset. Also the CLK pin is a digital input so any ESD diodes will be referenced to DVDD/DGND.

    Best regards,
    Chris