ADS1298: Leadoff detection throubles

Martin Echarri

Part Number: ADS1298

Sorry for make a new thread but the related question was locked. In the related question we made a question about the lead-off detection of ADS1298. About two months a TI employee said he was going to check it out but I think with the post locked is not posible.

Thanks.

Martin

over 2 years ago

0 Nick Zahabizadeh over 2 years ago

TI__Expert 4134 points

Hi Martin,

My apologies for us dropping your question! Could you link me the dropped thread? I'll personally oversee we get an answer for you.

Kind regards,
Nick

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hi Nick, thanks for your reply, the dropped thread is:
e2e.ti.com/.../ads1298-leadoff-detection-throubles

Regards,
Martin

0 Nick Zahabizadeh over 2 years ago in reply to Martin Echarri

TI__Expert 4134 points

Hi Martin,

Thanks for the response. Let me digest some information, and I'll get back to you with a response by Monday.

0 Nick Zahabizadeh over 2 years ago in reply to Nick Zahabizadeh

TI__Expert 4134 points

Hello Martin,

Could you share with us your register configuration and board schematics for your implementation of the ADS1298? We're doing some work on our side and want to compare.

Could you also check your register configuration on the ADS1298 EVM? This would be helpful for us to troubleshoot.

Kind regards,
Nick

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hello Nick, this is the used configuration:

ADS_Stop_Read_Data_Cont();

ADS_Write_register(ADS1298_CONFIG3_ADDR, VREFP_2 | PD_REFBUF_ON | RLD_BUF_ON | RLDREF_INT);

DelayMs(10); // no aclara cuanto esperar

ADS_Write_register(ADS1298_CONFIG1_ADDR, HR_ON | DAISY_OFF | CLK_OFF | DATA_RATE_MOD512); // High resolution, 1000SPS

ADS_Write_register(ADS1298_CONFIG2_ADDR, WCT_CHOP_VAR | INT_TEST_OFF | TEST_AMP1 | TEST_FREQ3);

ADS_Write_register(ADS1298_CH1SET_ADDR, PWR_UP | PGA_6 | CH_IN_NORMAL); // Normal mode

ADS_Write_register(ADS1298_CH2SET_ADDR, PWR_UP | PGA_6 | CH_IN_NORMAL); //Normal mode

ADS_Write_register(ADS1298_CH3SET_ADDR, PWR_DWN | PGA_6 | CH_IN_SHORTED);

ADS_Write_register(ADS1298_CH4SET_ADDR, PWR_DWN | PGA_6 | CH_IN_SHORTED);

ADS_Write_register(ADS1298_CH5SET_ADDR, PWR_DWN | PGA_6 | CH_IN_SHORTED);

ADS_Write_register(ADS1298_CH6SET_ADDR, PWR_DWN | PGA_6 | CH_IN_SHORTED);

ADS_Write_register(ADS1298_CH8SET_ADDR, PWR_DWN | PGA_6 | CH_IN_SHORTED);

ADS_Write_register(ADS1298_WCT2_ADDR,WCTB_ON|WCTB_CH1_NEG|WCTC_ON|WCTC_CH2_NEG);

ADS_Write_register(ADS1298_LOFF_ADDR, LOFF_COMP_THRES_1|VLEAD_OFF_PUP |LEAD_OFF_FREQ_4); // threshold 5% and 95%,detection with pull up resistors and DC lead off detection on

ADS_Write_register(ADS1298_CONFIG4_ADDR, LOFF_COMP_ON | WCT_TO_RLD_OFF); //Lead off comparator on, wilson is not to RL

ADS_Write_register(ADS1298_PACE_ADDR, PACE_CH2 | PACE_DETECT_BUFF_ON );

I think is understadable, but just in case I copy the meaning of every definition:

/******************************Bits asociados a CONFIG1*********************************************/

/* High resolution/Low power */

#define HR_ON 0x80 /*High resolution */
#define HR_OFF 0x00 /*Low Power*/

/* Daisy-hain / multiple readback*/

#define DAISY_ON 0x00 /*Daisy Chain mode*/
#define DAISY_OFF 0x40 /*Multiple Readback mode*/

/* CLK connection*/

#define CLK_ON 0x20 /*Oscillator Clock Output Disabled*/
#define CLK_OFF 0x00 /*Oscillator Clock Output Enabled*/

/* Output data rate*/

#define DATA_RATE_MOD16 0x00 /*32 KSPS en HR Mode; 16 KSPS en LP Mode*/
#define DATA_RATE_MOD32 0x01 /*16 KSPS en HR Mode; 8 KSPS en LP Mode*/
#define DATA_RATE_MOD64 0x02 /*8 KSPS en HR Mode; 4 KSPS en LP Mode*/
#define DATA_RATE_MOD128 0x03 /*4 KSPS en HR Mode; 2 KSPS en LP Mode*/
#define DATA_RATE_MOD256 0x04 /*2 KSPS en HR Mode; 1 KSPS en LP Mode*/
#define DATA_RATE_MOD512 0x05 /*1 KSPS en HR Mode; 500 SPS en LP Mode*/
#define DATA_RATE_MOD1024 0x06 /*500 SPS en HR Mode; 250 SPS en LP Mode*/

/*****************************Bits asociados a CONFIG2*********************************************/

/* WCT Chopping scheme*/

#define WCT_CHOP_VAR 0x00 /*Chopping frequency variable*/
#define WCT_CHOP_FIX 0x20 /*Chopping frequency fixed to FMOD/16*/

/* Test source*/

#define INT_TEST_ON 0x10 /*Test signal genrated internally*/
#define INT_TEST_OFF 0x00 /*Test signal driven externally (default)*/

/* Test signal amplitude*/

#define TEST_AMP1 0x00 /* 1 x -(VREFP- VREFN)/2400 V [default]*/
#define TEST_AMP2 0x04 /* 2 x - (VREFP - VREFN)/2400 V*/

/* Test siganl frequency*/

#define TEST_FREQ1 0x00 /*pulsed at fclk/2^21 [default]*/
#define TEST_FREQ2 0x01 /*pulsed at fclk/2^20 */
#define TEST_FREQ3 0x02 /* Not used*/
#define TEST_FREQ4 0x03 /* At dc*/

/********************************Bits asociados a CONFIG3*****************************************/

/*Power Down reference buffer*/

#define PD_REFBUF_OFF 0x40 /*Power down internal reference buffer [default]*/
#define PD_REFBUF_ON 0xC0 /*Enable internal reference buffer*/

/*Reference voltage*/

#define VREFP_2 0x40 /*VREFP set to 2.4V [default]*/
#define VREFP_4 0x60 /*VREFP set to 4V */

/*RLD MEasurement*/

#define RLD_MEAS_OFF 0x40 /*Open [deafult]*/
#define RLD_MEAS_ON 0x50 /*RLD_IN signal is routed to the channel that has the MUX_Setting 010(VREF)*/

/*RLDREF signal*/

#define RLDREF_INT 0x48 /*RLDREF signal (AVDD-AVSS)/2 generated internally*/
#define RLDREF_EXT 0x40 /*RLDREF signal fed externally [default]*/

/*RLD Buffer Power*/

#define RLD_BUF_ON 0x44 /*RLD Buffer is Enabled*/
#define RLD_BUF_OFF 0x40 /*RLD Buffer is Powered down [default]*/

/*RLD Sense function*/

#define RLD_SENS_ON 0x42 /*RLD Sens is enabled*/
#define RLD_SENS_OFF 0x40 /*RLD Sens is disabled [default]*/

/*RLD Lead off status*/

#define RLD_STAT_ON 0x40 /*RLD is connected [default]*/
#define RLD_STAT_OFF 0x41 /*RLD not connected*/

/***************Bits asociados a Lead Off control register***********************************/

/*Comp. pos. side - Comp. Neg. side*/
#define LOFF_COMP_THRES_1 0x00 /* 95% - 5% */
#define LOFF_COMP_THRES_2 0x20 /* 92.5% - 7.5%*/
#define LOFF_COMP_THRES_3 0x40 /* 90% - 10%*/
#define LOFF_COMP_THRES_4 0x60 /* 87.5% - 12.5%*/
#define LOFF_COMP_THRES_5 0x80 /* 85% - 15%*/
#define LOFF_COMP_THRES_6 0xA0 /* 80% - 20%*/
#define LOFF_COMP_THRES_7 0xC0 /* 75% - 25%*/
#define LOFF_COMP_THRES_8 0xE0 /* 70% - 30%*/

/*Lead off detection mode*/

#define VLEAD_OFF_CURR 0x00 /*Current source mode [default]*/
#define VLEAD_OFF_PUP 0x10 /*Pull up/ Pull down resistor mode*/

/*Lead off current magnitude*/

#define LEAD_OFF_MAG_1 0x00 /* 6 nA [default]*/
#define LEAD_OFF_MAG_2 0x04 /* 12 nA */
#define LEAD_OFF_MAG_3 0x08 /* 18 nA*/
#define LEAD_OFF_MAG_4 0x0C /* 24 nA*/

/*LEad off frequency*/

#define LEAD_OFF_FREQ_1 0x00 /*When any bits of the LOFF_SENSP or LOFF_SENSN register are turned on,
make sure that FLED[1:0] are either set to 01 0r 11 [default]*/
#define LEAD_OFF_FREQ_2 0x01 /*AC Lead-off detection at FDR/4*/
#define LEAD_OFF_FREQ_3 0x02 /*Not used*/
#define LEAD_OFF_FREQ_4 0x03 /*DC Lead-off detection turned on*/

/****************************************************************************************************/

/*******************CHnSET: Individual Channel Settings (n = 1 : 8)*********************************/

/*Power down*/

#define PWR_DWN 0x80 /*Channel powered down*/
#define PWR_UP 0x00 /*Normal Operation*/

/*Gain */

#define PGA_6 0x00 /*Gain = 6 [default]*/
#define PGA_1 0x10 /*Gain = 1*/
#define PGA_2 0x20 /*Gain = 2*/
#define PGA_3 0x30 /*Gain = 3*/
#define PGA_4 0x40 /*Gain = 4*/
#define PGA_8 0x50 /*Gain = 8*/
#define PGA_12 0x60 /*Gain = 12*/

/*MUX Channel Input*/

#define CH_IN_NORMAL 0x00 /*Normal Electrode input*/
#define CH_IN_SHORTED 0x01 /*Input shorted (for offset or noise measurement)*/
#define CH_IN_RLD_MEAS 0x02 /*used in conjunction with RLD_MEAS*/
#define CH_IN_MVDD 0x03 /*MVDD for supply measurement*/
#define CH_IN_TEMP 0x04 /*Temperature sensor*/
#define CH_IN_TEST 0x05 /*Test signal*/
#define CH_IN_RLD_DRP 0x06 /*RLD_DRP (positive electrode is the driver)*/
#define CH_IN_RLD_DRN 0x07 /*RLD_DRN (negative electrode is the driver)*/

/*****************************************************************************************************/

/*RLD_SENSP : This register controls the selection of the positive signal from each
channel for right leg drive derivation*/

#define RLD8P_ON 0x80
#define RLD8P_OFF 0x00

#define RLD7P_ON 0x40
#define RLD7P_OFF 0x00

#define RLD6P_ON 0x20
#define RLD6P_OFF 0x00

#define RLD5P_ON 0x10
#define RLD5P_OFF 0x00

#define RLD4P_ON 0x08
#define RLD4P_OFF 0x00

#define RLD3P_ON 0x04
#define RLD3P_OFF 0x00

#define RLD2P_ON 0x02
#define RLD2P_OFF 0x00

#define RLD1P_ON 0x01
#define RLD1P_OFF 0x00

/*****************************************************************************************/

/*RLD_SENSN : This register controls the selection of the negative signal from each
channel for right leg drive derivation*/

#define RLD8N_ON 0x80
#define RLD8N_OFF 0x00

#define RLD7N_ON 0x40
#define RLD7N_OFF 0x00

#define RLD6N_ON 0x20
#define RLD6N_OFF 0x00

#define RLD5N_ON 0x10
#define RLD5N_OFF 0x00

#define RLD4N_ON 0x08
#define RLD4N_OFF 0x00

#define RLD3N_ON 0x04
#define RLD3N_OFF 0x00

#define RLD2N_ON 0x02
#define RLD2N_OFF 0x00

#define RLD1N_ON 0x01
#define RLD1N_OFF 0x00

/*************************************************************************************/

/*LOFF_SENSP : This register select the positive side from each channel for lead- off
detection*/

#define LOFF8P_ON 0x80
#define LOFF8P_OFF 0x00

#define LOFF7P_ON 0x40
#define LOFF7P_OFF 0x00

#define LOFF6P_ON 0x20
#define LOFF6P_OFF 0x00

#define LOFF5P_ON 0x10
#define LOFF5P_OFF 0x00

#define LOFF4P_ON 0x08
#define LOFF4P_OFF 0x00

#define LOFF3P_ON 0x04
#define LOFF3P_OFF 0x00

#define LOFF2P_ON 0x02
#define LOFF2P_OFF 0x00

#define LOFF1P_ON 0x01
#define LOFF1P_OFF 0x00
/***************************************************************************************/

/*LOFF_SENSN : This register select the negative side from each channel for lead- off
detection*/

#define LOFF8N_ON 0x80
#define LOFF8N_OFF 0x00

#define LOFF7N_ON 0x40
#define LOFF7N_OFF 0x00

#define LOFF6N_ON 0x20
#define LOFF6N_OFF 0x00

#define LOFF5N_ON 0x10
#define LOFF5N_OFF 0x00

#define LOFF4N_ON 0x08
#define LOFF4N_OFF 0x00

#define LOFF3N_ON 0x04
#define LOFF3N_OFF 0x00

#define LOFF2N_ON 0x02
#define LOFF2N_OFF 0x00

#define LOFF1N_ON 0x01
#define LOFF1N_OFF 0x00
/**************************************************************************************/

/******************************** LOFF_FLIP ****************************************/

/* This register controls the direction of the current used for lead-off derivation*/

#define LOFF_FLIP8_ON 0x80
#define LOFF_FLIP8_OFF 0x00

#define LOFF_FLIP7_ON 0x40
#define LOFF_FLIP7_OFF 0x00

#define LOFF_FLIP6_ON 0x20
#define LOFF_FLIP6_OFF 0x00

#define LOFF_FLIP5_ON 0x10
#define LOFF_FLIP5_OFF 0x00

#define LOFF_FLIP4_ON 0x08
#define LOFF_FLIP4_OFF 0x00

#define LOFF_FLIP3_ON 0x04
#define LOFF_FLIP3_OFF 0x00

#define LOFF_FLIP2_ON 0x02
#define LOFF_FLIP2_OFF 0x00

#define LOFF_FLIP1_ON 0x01
#define LOFF_FLIP1_OFF 0x00

/***************************GPIO: General Purpose I/O Register**************************************/

#define GPIOC1_IN 0x01 /* IN [default]*/
#define GPIOC1_OUT 0x00 /* OUT */

#define GPIOC2_IN 0x02 /* IN [default]*/
#define GPIOC2_OUT 0x00 /* OUT */

#define GPIOC3_IN 0x04 /* IN [default]*/
#define GPIOC3_OUT 0x00 /* OUT */

#define GPIOC4_IN 0x08 /* IN [default]*/
#define GPIOC4_OUT 0x00 /* OUT */

/***************************************************************************************************/

/*************************************PACE: Pace Detect Register**************************************************************/

/* Pace Even Channels */

#define PACE_CH2 0x00 /*[Default]*/
#define PACE_CH4 0x08
#define PACE_CH6 0x10
#define PACE_CH8 0x18

/* Pace Odd Channels */

#define PACE_CH1 0x00 /*[Default]*/
#define PACE_CH3 0x02
#define PACE_CH5 0x04
#define PACE_CH7 0x06

/*Pace Detect Buffer*/

#define PACE_DETECT_BUFF_OFF 0x00 /*[Default]*/
#define PACE_DETECT_BUFF_ON 0x01

/******************************************************************************************************************************/

/****************************RESP: Respiration Control Register***********************************************************/

// #define RESP 0x00 /*[Default], no se usa en este chip*/

/**************************************************************************************************************************/

/********************************************Bits asociados a CONFIG4****************************************************************/

/*Respiration modulation frequency */

#define RESP_FREQ_64K 0x00 /*64 KHz modulation clock*/
#define RESP_FREQ_32K 0x20 /*32 KHZ modulation clock*/
#define RESP_FREQ_16K 0x40 /*16 kHz square wave on GPIO3 and GPIO4*/
#define RESP_FREQ_8K 0x60 /*8 kHz square wave on GPIO3 and GPIO4*/
#define RESP_FREQ_4K 0x80 /*4 kHz square wave on GPIO3 and GPIO4*/
#define RESP_FREQ_2K 0xA0 /*2 kHz square wave on GPIO3 and GPIO4*/
#define RESP_FREQ_1K 0xC0 /*1 kHz square wave on GPIO3 and GPIO4*/
#define RESP_FREQ_500 0xE0 /*500 Hz square wave on GPIO3 and GPIO4*/

/*Conversion mode*/

#define SINGLE_SHOT 0x04
#define CONT_MODE 0x00 /*[Default]*/

/*WCT to RLD Conection*/

#define WCT_TO_RLD_ON 0x04
#define WCT_TO_RLD_OFF 0x00 /*[Default]*/

/*Lead-Off comparator power down*/

#define LOFF_COMP_ON 0x02
#define LOFF_COMP_OFF 0x00 /*[Default]*/

/*********************************************************************************************************************/

/***********************WCT1: Wilson Terminal and Augmented Lead Control Register **********************************/

/* aVF_CH6: Enable (WCTA + WCTB)/2 to the negative input of channel 6*/

#define aVF_CH6_ON 0x80 /*Enable */
#define aVF_CH6_OFF 0x00 /*Disable [Default]*/

/* aVL_CH5: Enable (WCTA + WCTC)/2 to the negative input of channel 5*/

#define aVL_CH5_ON 0x40 /*Enable */
#define aVL_CH5_OFF 0x00 /*Disable [Default]*/

/* aVR_CH7: Enable (WCTB + WCTC)/2 to the negative input of channel 7*/

#define aVR_CH7_ON 0x20 /*Enable */
#define aVR_CH7_OFF 0x00 /*Disable [Default]*/

/* aVR_CH4: Enable (WCTB + WCTC)/2 to the negative input of channel 4*/

#define aVR_CH4_ON 0x10 /*Enable */
#define aVR_CH4_OFF 0x00 /*Disable [Default]*/

/* Power down WCTA*/

#define WCTA_ON 0x08 /*Powered On */
#define WCTA_OFF 0x00 /*Powered Down [Default]*/

/* WCT amplifier A channel selection ; typically connected to RA electrode*/

#define WCTA_CH1_POS 0x00 /*CH1 positive input connected to WCTA amp [Default]*/
#define WCTA_CH1_NEG 0x01 /*CH1 negative input connected to WCTA amp*/
#define WCTA_CH2_POS 0x02 /*CH2 positive input connected to WCTA amp*/
#define WCTA_CH2_NEG 0x03 /*CH2 negative input connected to WCTA amp*/
#define WCTA_CH3_POS 0x04 /*CH3 positive input connected to WCTA amp*/
#define WCTA_CH3_NEG 0x05 /*CH3 negative input connected to WCTA amp*/
#define WCTA_CH4_POS 0x06 /*CH4 positive input connected to WCTA amp*/
#define WCTA_CH5_NEG 0x07 /*CH5 negative input connected to WCTA amp*/

/********************************************************************************************/

/*****************WCT2: Wilson Terminal Control Register************************************/

/*Power down WCTC*/

#define WCTC_ON 0x80 /*Powered On */
#define WCTC_OFF 0x00 /*Powered Down [Default]*/

/*Power Down WCTB*/

#define WCTB_ON 0x40 /*Powered On */
#define WCTB_OFF 0x00 /*Powered Down [Default]*/

/*WCT amplifier B selection; typically connected to LA electrode */

#define WCTB_CH1_POS 0x00 /*CH1 positive input connected to WCTB amp [Default]*/
#define WCTB_CH1_NEG 0x08 /*CH1 positive input connected to WCTB amp */
#define WCTB_CH2_POS 0x10 /*CH2 positive input connected to WCTB amp */
#define WCTB_CH2_NEG 0x18 /*CH2 positive input connected to WCTB amp */
#define WCTB_CH3_POS 0x20 /*CH3 positive input connected to WCTB amp */
#define WCTB_CH3_NEG 0x28 /*CH3 positive input connected to WCTB amp */
#define WCTB_CH4_POS 0x30 /*CH4 positive input connected to WCTB amp */
#define WCTB_CH4_NEG 0x38 /*CH5 positive input connected to WCTB amp */

/*WCT amplifier C selection; typically connected to LL electrode */

#define WCTC_CH1_POS 0x00 /*CH1 positive input connected to WCTC amp [Default]*/
#define WCTC_CH1_NEG 0x01 /*CH1 positive input connected to WCTC amp */
#define WCTC_CH2_POS 0x02 /*CH2 positive input connected to WCTC amp */
#define WCTC_CH2_NEG 0x03 /*CH2 positive input connected to WCTC amp */
#define WCTC_CH3_POS 0x04 /*CH3 positive input connected to WCTC amp */
#define WCTC_CH3_NEG 0x05 /*CH3 positive input connected to WCTC amp */
#define WCTC_CH4_POS 0x06 /*CH4 positive input connected to WCTC amp */
#define WCTC_CH4_NEG 0x07 /*CH4 positive input connected to WCTC amp */

/*********************************************************************************************/

/******************************** Opcodes Commands Definitions ********************************/

/* System Commands */

#define ADS_WAKEUP 0x02 /*Wake up from stand by mode*/
/*cualquier comando subsiguiente tiene que ir despues de 4tclk */
#define ADS_STANDBY 0x04 /*Enter stand by mode*/
#define ADS_RESET_CMD 0x06 /*Reset the device*/
/*se necesitan 18 tclk para el reset. no enviar comandos mientras tanto*/
#define ADS_START 0x08 /*Start/restart (synchronize) conversions*/
#define ADS_STOP 0x0A /*Stop conversion*/

/* Data Read Commands */

#define ADS_RDATAC 0x10 /*Enable Read data continuous mode*/
/*This mode is the dafault mode at power up*/
#define ADS_SDATAC 0x11 /*Stop read data continuously mode*/
#define ADS_RDATA 0x12 /*Read data by command; supports multiple readback*/

/* Register Read Commands */

#define RREG
#define WREG

/******************** Address Registers ********************************************/

/* Global Settings Across Channels*/

#define ADS1298_CONFIG1_ADDR 0x01
#define ADS1298_CONFIG2_ADDR 0x02
#define ADS1298_CONFIG3_ADDR 0x03
#define ADS1298_LOFF_ADDR 0x04

/* Channel Specific Settings*/

#define ADS1298_CH1SET_ADDR 0x05
#define ADS1298_CH2SET_ADDR 0x06
#define ADS1298_CH3SET_ADDR 0x07
#define ADS1298_CH4SET_ADDR 0x08
#define ADS1298_CH5SET_ADDR 0x09
#define ADS1298_CH6SET_ADDR 0x0A
#define ADS1298_CH7SET_ADDR 0x0B
#define ADS1298_CH8SET_ADDR 0x0C
#define ADS1298_RLD_SENSP_ADDR 0x0D
#define ADS1298_RLD_SENSN_ADDR 0x0E
#define ADS1298_LOFF_SENSP_ADDR 0x0F
#define ADS1298_LOFF_SENSN_ADDR 0x10
#define ADS1298_FLIP_ADDR 0x11

/*Lead-Off Status Register (Read Only Registers)*/

#define ADS1298_LOFF_STATP_ADDR 0x12
#define ADS1298_LOFF_STATN_ADRR 0x13

/*GPIO and Other Registers*/

#define ADS1298_GPIO_ADDR 0x14
#define ADS1298_PACE_ADDR 0x15
#define ADS1298_RESP_ADDR 0x16
#define ADS1298_CONFIG4_ADDR 0x17
#define ADS1298_WCT1_ADDR 0x18
#define ADS1298_WCT2_ADDR 0x19

I will send and schematic in a while.

Regards

Martin

0 Martin Echarri over 2 years ago in reply to Martin Echarri

Prodigy 80 points

Now I attach the sintetic schematic:

Regards,

Martin

0 Nick Zahabizadeh over 2 years ago in reply to Martin Echarri

TI__Expert 4134 points

Hello Martin,

Thanks for the detailed information. We'll take a look and let you know within 36 hours.

Kind regards,
Nick

0 Nick Zahabizadeh over 2 years ago in reply to Nick Zahabizadeh

TI__Expert 4134 points

Hello Martin,

Just letting you know we're working on a solution, we're double-checking if it fits your register configuration. Thank you for your patience.

Kind regards,
Nick

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hello Nick,

Thanks for the response. I will be attentive to the news.

Kind regards,

Martin

+1 Nick Zahabizadeh over 2 years ago in reply to Nick Zahabizadeh

TI__Expert 4134 points

Hello Martin,

Please try making sure that Lead-off sensing is on for all channels (LOFFP and LOFFN), and try RLD open, this stabilized the inputs on our end.

Another note: your code does not have a ADS_Write_register() for channel 7, which may be leading to the leads-off detection problems for that channel.

Kind regards,
Nick

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hello Nick, sorry I mark involuntarily your answer as "this resolve my issue" but we have not tried yet. ASAP we can try your sugestion we post the results.

Javier Mendieta

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hello Nick,

In order to check, when you said "try RLD open". Did you mean disconnect the RL lead or change the configuration of the RLD amplifier and power off?

Kind regards,

Martin

0 Nick Zahabizadeh over 2 years ago in reply to Martin Echarri

TI__Expert 4134 points

Hello Martin,

My apologies for my poor clarification. To set RLD to open, please try setting RLD_MEAS (bit 4) in CONFIG3 register to 0.
Also, please as well as VLEAD_OFF_EN (bit 4) in LOFF register to 1 for resistor pullup/pulldown mode.

Let me know how this goes for you.

Kind regards,
Nick

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hello Nick,

We will try the configurations you describe, but we tried RL disconnected and RL connected. I send you this tests while we try yours recomendations.

We put on all the LOFFP and LOFFN on and added the channel 7 configuration (we used the same configuration than channels 3,4,5,6 and 8).

We disconnected the RL lead and the result was:

LL (IN2N)		RA (IN1P and IN2P)		LA (IN1N)
Lead	AFE Indication		AFE Indication		AFE Indication
Connected	0	Connected	0	Connected	0
Disconnected	1	Connected	0	Connected	0
Connected	1	Disconnected	1	Connected	1
Connected	0	Connected	0	Disconnected	1
Disconnected	1	Disconnected	1	Connected	1
Disconnected	1	Connected	1	Disconnected	1
Connected	1	Disconnected	1	Disconnected	1
Disconnected	1	Disconnected	1	Disconnected	1

In the table "lead" indicated the lead status and "AFE indication" is the bit of status word correspondent to the ADS1298 input. In red are marked the misindications.

Later we reproduce the test with RL lead connected, and the result was:

LL (IN2N)		RA (IN1P and IN2P)		LA (IN1N)
Lead	AFE Indication		AFE Indication		AFE Indication
Connected	0	Connected	0	Connected	0
Disconnected	1	Connected	0	Connected	0
Connected	0	Disconnected	1	Connected	0
Connected	0	Connected	0	Disconnected	1
Disconnected	1	Disconnected	1	Connected	0
Disconnected	1	Connected	1	Disconnected	1
Connected	0	Disconnected	1	Disconnected	1
Disconnected	1	Disconnected	1	Disconnected	1

Then we have with RL connected 1 misindications and with RL disconnected 5 misindications.

We noted LL (IN2N) lead off indication was late (1 or 2 seconds) when RL was disconnected but when RL was connected the LA (IN1N) lead off indication was late (1 or 2 seconds).

We will try the recommended RLD configuration.

Regards

Martin

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hello Nick,

The RLD_MEAS (bit 4) in CONFIG3 register is on 0 by default but we put it in 0 by configuration in order to verify. The VLEAD_OFF_EN (bit 4) in LOFF register to 1 for resistor pullup/pulldown mode is configurated in this line:

ADS_Write_register(ADS1298_LOFF_ADDR, LOFF_COMP_THRES_1|VLEAD_OFF_PUP |LEAD_OFF_FREQ_4);

Where VLEAD_OFF_PUP is 0x10, then the bit 4 is 1 and is setted to pullup/pulldown resistors.

The test results are the same as the previous post. We tested with RL connected and disconnected again.

Regrads

Martin

0 Nick Zahabizadeh over 2 years ago in reply to Martin Echarri

TI__Expert 4134 points

Hi Martin,

Thanks again for the great info. We're currently looking into it, please give us a day or two for internal discussion and testing.

Kind regards,
Nick Z

0 Nick Zahabizadeh over 2 years ago in reply to Nick Zahabizadeh

TI__Expert 4134 points

Hello Martin,

We spent some time experimenting.

That 'late' nature you experienced of lead off detection makes sense, it takes a little time for the signal to saturate up or down in order for the AFE to know that the lead is off.

At first glance, our most stable results was when we configured the RLD to be a unity gain buffer; set all the LOFF bits to 0, and keep the RLD powered on. Please set the Gain of each channel equal to 1 (set GAINn bits to 001 in CHnSET, datasheet section 9.6.1.6) . We're going analyze some of the data and let you know more next week.

Kind regards,
Nick

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hello Nick, We don't understand what you mean, because if we put all OFF in 0 there in not Lead Off detection which is what we want to test

We don't understand what you mean with unity gain. We are using the circuit of figure 58 cof datasheet (page 62). We can change the resistor for gain -1. Or letf open all the RLD_SENS_P and RLD_SENS_N, change the resistor to 0 Ohm and then we have unity gain for internal reference in RLD, in this option RLD amplifier has not leads information.

We tried the second option (unity gain for internal reference) in the past (but with the 1MOhm resistor) and the result was the same.

Kind regards,

Martin

0 Nick Zahabizadeh over 2 years ago in reply to Martin Echarri

TI__Expert 4134 points

Hi Martin,

My apologies, you are correct, since you are looking to keep Leads-Off Detection. With that in mind, please let me know how setting the gain to 1 helps. Since the programmable gain is configured via register, you don't need to modify any resistors.

"We are using the circuit of figure 58 of datasheet (page 62)" -- I am confused, figure 58 of the ADS1298 datasheet points to the DRDY signal, and page 62 talks about timing. In which manner is your circuit configured?

Kind regards,
Nick

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hi Nick,

Sorry I referred to an old datasheet. In the last datasheet is page 34, figure 33.
We will test the unity gain and will be back with the results.
Kind regards,
Martin

0 Martin Echarri over 2 years ago in reply to Martin Echarri

Prodigy 80 points

Hi Nick,

We test the unity gain in PGA's and the result was the same as gain = 4.

We are thinking about that if we disconnect the two pull downed leads the pull uped lead says the lead is disconnected instead are connected. Could be the fact that RA is connected to two inputs affect the lead off detection?

Kind regards,

Martin

0 Nick Zahabizadeh over 2 years ago in reply to Martin Echarri

TI__Expert 4134 points

Hi Martin,

When testing with the different gain, what did the output waveform of the ADC look like?
There should be a difference between the two gain settings.

Kind regards,
Nick

0 Martin Echarri over 2 years ago in reply to Nick Zahabizadeh

Prodigy 80 points

Hi Nick,
The only one difference between gain 4 and 1 is the amplitude of measured waveform, but the lead off situation is the same as before.

Kind regards,

Martin

0 Nick Zahabizadeh over 2 years ago in reply to Martin Echarri

TI__Expert 4134 points

Hi Martin,

You are absolutely correct. However, we just want to make sure that without RLD, Leads off, or any other part of the signal chain what the waveform looks like so we can better troubleshoot.

Let's host a call so we can better dedicate support versus these two threads. I'm going to reach out via email.

Kind regards,
Nick Z

0 Nick Zahabizadeh over 2 years ago in reply to Nick Zahabizadeh

TI__Expert 4134 points

Hi Martin,

Since this conversation was taken to email and a meeting to solve the problem, I'll be closing the thread. Please reply on our email thread for anything following this topic.

Kind regards,
Nick Z

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ADS1298: Leadoff detection throubles