• State TI Thinks Resolved
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 542 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DAC38RF82EVM: How do I solve the initialization failure

XIaodie Hu
Prodigy 100 points
Part Number: DAC38RF82EVM
Other Parts Discussed in Thread: LMK04828, TSW14J57EVM, DAC38RF82

Hello!

Is the hardware setting of "on-board VCXO clock mode" On DAC38RF82EVM like this?

I used jumper caps to connect pins 2 and 3 of JP1、 pins 1 and 2 of JP2、 pins 1 and 2 of JP3, but not pins 1 and 2 of JP10.

However, after clicking "Not in RESET" and "LOAD DEFAULAT" of the software DAC38RF8xEVM GUI, it shows that " Initiialization failed. Possible reasons are no clock detected or device is in sleep.1)For On-chip PLL mode, enable clock source (4dBm)to SMAJ4 and remove shunt on JP10;2)For external clock mode ,enable clock source (16dBm)to SMA J1 and install shunt on JP10;3)Check/ Install shunt on JP1，pins 2and 3,JP2,pins 1 and 2, How to solve it?.

  • 0
    TI__Mastermind 23780 points

    Hi Xlaodie,

    The hardware settings are correct. What you are seeing is expected as the default configuration loaded by Load Default expects the DAC PLL reference clock frequency to be applied to J4 directly. This message can be considered a warning and not as an error as you are intentionally trying to operate without any external signal to the EVM board.

    If you do not care about synchronization for now, you can use the onboard VCXO by choosing settings on the LMK04828 PLL1 Configuration and PLL2 Configuration pages. The onboard VCXO reference oscillator is 122.88MHz so you will only be able to generate frequencies which are integer multiples of this value. Keep this in mind when selecting a DAC CLK frequency. Below is an example of how to generate a 2949.12MHz clock as the LMK04828 output VCO frequency. The following image shows this 2949.12MHz VCO1 frequency being divided down to 245.76MHz on the Clock Outputs tab which provides the DAC PLL reference clock.

    If you need help with configuring the LMK04828 for any specific frequency multiple of 122.88MHz, please feel free to reach back out.

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 100 points

    Hi Chase,

    1,Combined with TSW14J57EVM, I only use the "on-board VCXO clock mode" of DAC38RF82EVM. What is the frequency range of sinusoidal signals generated by DAC38RF82EVM? How to use the "on-board VCXO clock mode" of DAC38RF82EVM ?

    2,When using the "on-board VCXO clock mode" of DAC38RF82EVM,can I set the "DAC MODE"   as follows to generate a 4.5GHz sinusoidal signals? What means about "real input"of the #of IQ pairs# ?

  • 0 in reply to Chase W
    Prodigy 100 points

    Hi Chase,

    I want to use the "on-board VCXO clock mode" of DAC38RF82EVM,but it shows like this photo. And I have tried the Settings you mentioned above  on the LMK04828 PLL1 Configuration and PLL2 Configuration pages, but it no works. I can't use the HSDC Pro GUI to generate a tone ,and the LED D2(TSW14J57EVM) cannot flicker.

  • 0 in reply to XIaodie Hu
    TI__Mastermind 23780 points

    Hi Xlaodie, please see my comments below.

     

    XIaodie Hu said:
    Combined with TSW14J57EVM, I only use the "on-board VCXO clock mode" of DAC38RF82EVM. What is the frequency range of sinusoidal signals generated by DAC38RF82EVM?

    The frequency range which the TSW14J57EVM can supply to the DAC38RF82EVM is dependent on the sample rate and interpolation factor of the DAC operating mode. The minimum frequency is always 0Hz, the maximum frequency is calculated as below in order to satisfy Nyquist theorem.

    When this is combined with the integrated NCO of the DAC38RF82, the output frequency can reach beyond Fs/2 but careful frequency planning is necessary as aliasing is centered around fDAC/2. 

     

     

    XIaodie Hu said:
    How to use the "on-board VCXO clock mode" of DAC38RF82EVM

    See this presentation which goes through example of setting LMK04828 PLL2. DAC38RF82EVM_OnboardClocking_6144MSPS_LMF841.pptx

     

     

    XIaodie Hu said:
    When using the "on-board VCXO clock mode" of DAC38RF82EVM,can I set the "DAC MODE"   as follows to generate a 4.5GHz sinusoidal signals?

    Yes, this mode LMFS = 8118 is a meant for wideband signal applications. The FPGA will be able to send any combination of signals between 0Hz and 4.5GHz without the use case of the NCO. This allows for incredible flexibility in data patterns. For a single frequency narrowband output, this is not the best mode.

      

     

    XIaodie Hu said:
    What means about "real input"of the #of IQ pairs# ?

    Real input refers to modes where the incoming data pattern should consists only of the in-phase component (just the I) of an IQ signal pair.

     

     

    There are many issues with the two softwares in the images you've posted above. Before I address and comment on these issues, I must know of the signal bandwidth requirements. This will allow me determine the best operating mode for your application. I understand you desire an output at 4.5GHz, but do you only need a single continuous waveform sinusoid or multiple sinusoids?

     

    Please refer to these presentations as well for more info:

     

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 100 points

    Hi Chase,

    Merry Christmas ! Thank you very much, I learned a lot.

    1,I want to get as high a frequency output as possible. This requires a higher "data rate(SPS)". And a higher "DAC Clock Frequency" and a lower " Interpolaton", such as the mode of "LMF=811". Could you teach me about "PLL2 Configuration" and "Clock Outputs" of mode of "LMF=811" "on-board VCXO clock mode" of DAC38RF82EVM ? If I can, I need more configuration in other "LMF" modes.

    2,I want to use HSCD Pro GUI load file to generate a square wave signal with a different frequency. As shown below:

  • 0 in reply to XIaodie Hu
    TI__Mastermind 23780 points

    Hi Xlaodie,

    Thanks for the well wishes. I won't be able to test and provide a config file for your desired mode until returning to work next week, however please look through this presentation which I created a few months ago explaining the basics of the LKM04828 device (from the perspective of our EVM) as well as show some examples for setting the PLL2 Configuration tab.

    LMK04828 Fundamentals.pptx

    Regards, Chase

  • 0 in reply to Chase W
    Prodigy 100 points

    Hi Chase,

    According to the information you provided, I will study it first. Wish you a happy holiday!