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TX7332EVM: Suggestion for previous solution provided by TI

Part Number: TX7332EVM
Other Parts Discussed in Thread: TX7332,

Hello E2E Experts,

Good day.

As a continuation of the previous E2E inquiry, below are our concerns: TX7332EVM: Needs Urgent Suggestion - Data converters forum - Data converters - TI E2E support forums

(1) How to trigger externally the tx7332 board for data acquisition process, is there any pin used for external triggering in tx7332 pulser board?which pin of tx7332 has to send trigger pulse, which in turn pulsate the tx-rx switch for receiving signal?

(2) During hardware setting, it generates a two cycle pulsed signal at tx pin of tx7332evm by default. how to generate a single pulse instead of two.?

Your answer:

To generate a single cycle, you need to keep the Repeat Count = 0.

 Currently, the device is running with a BF_CLK frequency of 200MHz. The frequency can be reduced by writing CLK_DIV = 5. This will reduce the clock to 200/32 = 6.25MHz (160ns). The maximum number of transitions possible is 16, which gives a maximum of 8 transitions per level. The period can be set to an utmost of 30, which gives 32 clocks per period. In this case, we can get a maximum level duration of 32*8*160ns = 40960ns. This will be around 12kHz.

***However, I am getting single cycle pulse signal TR_BF_SYNC pin and pulser output that was fine, but it was in Khz range, which is not helping me. I need in between 100-300hz. I am actually trying to get the TR_BF_SYNC signal in between 100hz-300hz, which i want to use as trigger signal for hardware device. Also the pulser output signal at tx_out pin should come in this range, but its a high voltage signal

***In your second suggestion, u told to get frequency below that u need to 

Remove R19 and R20 resistors.

- Connect R17 and R23 resistors.

Feed the clock at J3

Using the above, you should be able to get a low-frequency output., if you feed in a clock of 10MHz and use the maximum CLK_DIV factor of 5.

*** I remove and connect as per ur suggestion and apply an external clock signal of 1MHZ of 2v peak-peak clock signal at J3, but i am not getting any pulsed signal at TR_BF_SYNC pin as well as pulser output, getting a noisy output. Again the problem it is showing, i am giving a 2v peak-peak clock signal, but at the R23 register, i am getting only 100mv amplitude, a signal loss occurs. Again u have told set clock division factor to 5, as I am giving my clock signal externally and have already disconnected my crystal oscillator from the circuit by removing R19 and R20, how this can be set through that tx7332 GUI, will it work?

Regards,

CSC

  • Additional Information:

    I am giving a 1mhz dc clock of 2v peak-peak at port j3, but as i am giving a dc clock signal, so it is blocked by capacitor(c63), so no output at sync pin as well as pulser output pin. Do i need to give dc clock signal or AC signal at port j3. Now i am getting a 1v peak-peak signal at resistor R23, it is due to two 50ohm register, but after that there is no signal going to the output. i need TR_BF_SYNC signal in between 100-300 hz and pulser output a high voltage signal in same frequency range(100-300hz) or more than that.

    Regards,

    CSC

  • Hi,

    We have to feed in a signal with 0 dc. Could you try increasing the amplitude of the signal fed to 3Vpp (at the R23)? Could you probe the signals you are able to get at the pins 2 and 3 of the U5 buffer? Are these signals coming fully differential? 

    Regards

    Savyan

  • Hello Savyan,

    Good day.

    Now I am getting an output signal for the same input, i was trying before. signal I am getting of 5HZ around. I need to bring it to 100hz-300hz. I am not giving any commands through GUI. I am controlling through hardware. But there is a lot of delay between the sync signal and pulser output at 1mhz (2v ,p-p). As we increase frequency delay is decreasing but the signal is very noisy. I want to know whether, now the board will work through GUI or not, As we have disconnected the crystal oscillator.

    Regards,

    CSC

  • Hi,

    The delay from the SYNC to the output depends on the value programmed in the memory for the channel delay. If 'N' is programmed as the channel delay, then the delay is expected to be in the order of 'N' clocks. So, when you change the clock frequency, the delay is also expected to change. There will also be other components to the delay which have dependence on the clock frequency. As for the controlling the device through the GUI, it will still be possible to control it irrespective of whether the clock comes from the external world or the crystal.

    Regards

    Savyan