DAC53004: Setting time becomes larger with low output voltage

Hi Aurélie,

The DAC output is not driving any current. The gate of a NMOS draws no current so the DAC output should not be struggling to drive anything. As the voltage across the 1300R resistor gets smaller, then the Vs voltage of the NMOS gets closer to 9V. Can you check that the FET you are using supports this? Also please share the rest of your schematic. if there are any capacitors in the circuit they could be contributing to charging/discharging as the voltage across 1300R changes. 

Best,

Katlynne Jones 

Hi Katlynne,

I am using the N-MOS SSM3K35CTC,L3F which can handle 20V, it should not be the issue then.

There are no capacitor in the FB/OUT loop, but we are using DC blocking cap across the load (I have also performed test without them and the results are the same):

I have performed measurement where I removed the mosfet. I have placed a resistive divider between OUT and FB to have an OUT higher than the FB, like in my circuit:

I have send the command DAC_DATA = 28 (for 50mV on FB and around 550mV on OUT) and here is what I see:

Pink: Command that triggers the pulse; Green: OUT; Yellow: FB

This is alright. I have then did the same thing with DAC_DATA = 16 (28mV on FB and around 300mV on OUT):

Here you can see that there is an issue. I think there is a limitation/minimum VFB, or there is something else that I don't get.

This is critical for our project as we need to be able to reach very low current into our load.

Best Regards,

Aurelie

Hi Aurelie,

You have the blocking caps C25 and C26 connected to the source of each NMOS, but where is the 1300R load connected? 

Best,

Katlynne Jones 

Hi Katlynne,

My bad, it is connected between E1 and E2.

Best Regards,

Aurelie Duval

Hi Aurelie,

Originally you said the settling time became longer, but it looks like there is a delay in the voltage increasing after the rising edge of the pink trigger pulse. You replaced the NMOS with the resistor divider between OUT and FB, but is the rest of the circuit still there? I wouldn't expect this behavior to come from just this circuit:

Best,

Katlynne Jones 

Hi Katlynne,

The rest of the circuit isn't there anymore, I have disconnected everything and the only things connected are now the 47k and the 4k7. Is there maybe any internal capacitance that needs to be charged?

Best Regards,

Aurelie Duval

Hi Aurelie,

Got it, thanks for clarifying. We have a pspice model for the DAC53701 which has a similar output stage to the DAC63204. Let me try to simulate this and also ask the design team if they have an opinion on the behavior. There will likely be a delay in their response, so I'll get back to you as soon as I hear back. 

Best,

Katlynne Jones

Hi Katlynne,

Did you simulate the behaviour of the DAC53701 on pspice?

Best,

Aurelie Duval

Hi Aurelie,

This is the behavior I'm seeing in the simulation with a 40us on time and 10us off time:

50mV setting:

28mV setting:

It looks like the output does not have enough time to fall to 0V, but I'm not noticing the delay that you show in your plots. I can also try to check on a DAC63204EVM to see if I see anything closer to your results. 

Best,

Katlynne Jones

Hi Katlynne,

Thank you for performing the simulation.

The U5(IN) is the signal that triggers the OUT signal?

I have tested again on my board to be sure I haven't done anything wrong but I still observe the same issue when the FB voltage gets lower.

I am using the DAC63204EVM but I have soldered the DAC53004 instead. Do you have the possibility to try that as well? So we can really compare the same setup.

Best Regards,

Aurélie

Hi Aurelie,

Yes, U5 is an ideal ADC model that we can wire to the digital inputs of the DAC model. U5_IN tells the ADC what code to write to the DAC. 

Just to be sure, are you writing these codes via I2C/SPI or using the GPI input to switch the codes? I don't have a DAC53004 on hand, but the output stage is the exact same as the DAC63204 so I can try on my EVM. Can you let me know what reference you're using (internal and gain setting, or external) and the codes you are writing so I can use the same settings?

Best,

Katlynne Jones 

Hi Katlynne,

I am writing these code via SPI.

We are using internal reference and 1.5 gain.

I am not the one that designed the software, but here is the driver my colleague wrote. Is that what you need?

#include "hal_dac63004.h"

#include "board_config.h"
#include "nrfx_spim.h"
#include "nrfx_ppi.h"
#include "nrfx_gpiote.h"
#include "error.h"
#include "log.h"

#define STEPS (30)

typedef struct {
    uint8_t data[STEPS][3];
} hal_dac63004_t;

static hal_dac63004_t hal_dac63004;
static const nrfx_spim_t spim3 = NRFX_SPIM_INSTANCE(0);

static void dac_data_write(uint8_t *d, const hal_dac63004_data_t *data)
{
    static const uint8_t channel_conv_table[] = { 0x19, 0x1a, 0x1b, 0x1c };
    d[0] = channel_conv_table[data->channel];
    d[1] = (data->value >> 2);
    d[2] = (data->value << 6);
}

static void spim_handler(nrfx_spim_evt_t const *p_event, void *p_context)
{
}

static uint32_t setup_spim(void)
{
    static const nrfx_spim_config_t config = {
        .sck_pin = BOARD_DAC63004_SCK_PIN,
        .mosi_pin = BOARD_DAC63004_MOSI_PIN,
        .miso_pin = NRFX_SPIM_PIN_NOT_USED,
        .ss_pin = BOARD_DAC63004_SS_PIN,
        .ss_active_high = false,
        .irq_priority = 6,
        .orc = 0xca,
        .frequency = NRF_SPIM_FREQ_8M,
        .mode = NRF_SPIM_MODE_0,
        .bit_order = NRF_SPIM_BIT_ORDER_MSB_FIRST,
    };
    nrfx_err_t err_code = nrfx_spim_init(&spim3, &config, spim_handler, NULL);
    assert_param(NRFX_SUCCESS == err_code);
    static const nrfx_spim_xfer_desc_t xfer = {
        .p_tx_buffer = (uint8_t const *) hal_dac63004.data,
        .tx_length = 3,
        .p_rx_buffer = NULL,
        .rx_length = 0,
    };
    err_code = nrfx_spim_xfer(&spim3, &xfer,
                              (NRFX_SPIM_FLAG_TX_POSTINC | NRFX_SPIM_FLAG_HOLD_XFER | NRFX_SPIM_FLAG_REPEATED_XFER |
                               NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER));
    return nrfx_spim_start_task_get(&spim3);
}

static uint32_t setup_trigger(void)
{
    static const nrfx_gpiote_in_config_t config = {
        .sense = NRF_GPIOTE_POLARITY_HITOLO,
        .pull = NRF_GPIO_PIN_PULLUP,
        .is_watcher = false,
        .hi_accuracy = true,
        .skip_gpio_setup = true,
    };
    nrfx_err_t err = nrfx_gpiote_init();
    nrf_gpio_cfg_input(BOARD_TRIGGER_IN_PIN, config.pull);
    assert_param(NRFX_SUCCESS == err);
    err = nrfx_gpiote_in_init(BOARD_TRIGGER_IN_PIN, &config, NULL);
    assert_param(NRFX_SUCCESS == err);
    nrfx_gpiote_in_event_enable(BOARD_TRIGGER_IN_PIN, false);
    return nrfx_gpiote_in_event_addr_get(BOARD_TRIGGER_IN_PIN);
}

static void setup_ppi(uint32_t tep, uint32_t eep)
{
    nrf_ppi_channel_t channel;
    nrfx_err_t err = nrfx_ppi_channel_alloc(&channel);
    assert_param(NRFX_SUCCESS == err);
    err = nrfx_ppi_channel_assign(channel, eep, tep);
    assert_param(NRFX_SUCCESS == err);
    err = nrfx_ppi_channel_enable(channel);
    assert_param(NRFX_SUCCESS == err);
}

void hal_dac63004_init(void)
{
    const uint32_t tep = setup_spim();
    const uint32_t eep = setup_trigger();
    setup_ppi(tep, eep);
}

void hal_dac63004_send(const hal_dac63004_data_t *data, size_t len)
{
    assert_param(data != NULL);
    assert_param(len <= STEPS);
    for (size_t k = 0; k < len; k++) {
        dac_data_write(hal_dac63004.data[k], &data[k]);
    }
    spim3.p_reg->TXD.PTR = (uintptr_t) hal_dac63004.data[0];
}

Best,

Aurelie Duval

Hi Aurelie,

Thanks for confirming the internal reference with 1.5x gain. I just needed to know which output codes you wanted me to test. But I'll try to replicate your images here using the internal reference with 1.5x gain:

Best,

Katlynne Jones 

Hi Katlynne,

I was having issue with output code between 10 and 50.

Best,

Aurélie Duval

Hi Aurélie,

Ok, I will try a few output codes in that range as well as larger ones. I'll have time to set this up in the lab on Monday, so I will back to you with my results by then.

Best,

Katlynne Jones 

Hi Aurélie,

I'm starting at code 0 and writing code 64 (0x40) to the DAC output using the internal reference with 1.5x gain. I have a 47k and 4.7k resistor configured in a voltage divider as shown in your schematic. I do not see any delay from the last SCL edge (blue) and the output starting to rise. OUT is yellow and FB is pink. 

I am using a 12-bit device (DAC63204) so I adjusted the data to output the 300mV you were seeing.

I also tried code 16 (0x10) and did not see an issue there either:

Is it possible your device is damaged? 

Best,

Katlynne Jones 

Hi Aurelie,

I will try to do this test as well on my own and bring it up with the design team to see if this behavior is expected on the design side. They do share the exact same output stage so it is strange that they would behave differently. 

Best,

Katlynne Jones