DAC37J82: No output issue_2

JH,

1. What are the LMFS settings used?

2. What output channels do they plan on using? Any of the four are available but only two input data paths are allowed.

3. If using the TI EVM, send screen shots of the GUI with their setup.

Regards,

Jim

Jim,

Here are the customer responses.

1.: 4211

-. Added setting information

DAC Data Rate input : 983.04Mhz

Interpolation : 1

Dac Output rate : 983.04Mhz

FPGA Jesd CLK : 245.76Mhz

Jesd Line Rate : 9.8304Ghz

Path setting : config34, (1B39)

Sample 0  -> Path a  -> DAC A

Sample 1  -> Path b  -> DAC D

Sample 2  -> Path c  -> DAC C (sleep)

Sample 3  -> Path d  -> DAC B (sleep)

2. : A & D DAC (2ea)

Any of the four are available but only two input data paths are allowed.

: DAC input : Rx0, Rx1, Rx2, Rx3 (Rx4~Rx7 not used), output A / D (B/C dac sleep)

3. : Unfortunately, we use our own board. Please refer attachment(cfg file) except lmk04808 register. (it’s hard typing our dac register writing)

cfg file is attached. Please refer to the DAC settings only.

421_CHA_CHD_230614_register.cfg

Thank you.

JH

JH,

Try this attached config file for the DAC. This use a K of 20 and SYSREF frequency of 6.144MHz. All other parameters match the ones mentioned above. 

Regards,

Jim

DAC37J82_4211_983.04_CHA_CHD.cfg

Hi Jim,

Here is the customer's answer.

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After changing to K=20, SYSREF=6.144MHz, I tested it, but the result is the same.

If the value of Config77 (0x4D, Number of converters per link) is 0x0001, both outputs do not come out, and if it is 0x0003, A output comes out.

Please answer whether it is correct to set 0x0003 even when using Dual CH.

For reference, our current k setting is 32, and SYSREF is 3.84Mhz.
  SYSREF = 9.8304GHz (line rate) / (32(K)*80(N)) = 3.84MHz

If I set 0x4D to 0x0003 with the above setting value, DAC A Output comes out.
Additional: SYSREF Alarm OK (DAC Register Alarm 0x6C), Line Alignment OK (DAC Register Alarm 0x64, 0x65, 0x66, 0x67)

I think that the reason why the D output is not coming out is the Path setting problem. Please comment on this.

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Regards,

JH

JH,

Config77 (0x4D) needs to be 0x100. The value entered into the register for M is M-1. For F, the value entered is F-1.

So with LMF = 421, M= 2 and F = 1.

M-1 = 2-1 = 1. So bits 15:8 = 00000001 

F-1 = 1-1 = 0. So bits 4:0 = 0000

Bits 7:5 are reserved and set to 000. 

So address 0x4D should be 0000 0001 0000 0000 = 0x0100.

This is the value present in the configuration file I sent.

Regards,

Jim 

Hi Jim,

Here is the customer answer.

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I agree with your comment that 0x0001 should be written for 0x4D.
Since M=2, I thought 0x0001 was correct. However, in the setting of 0x0001, there is no output.
It was confirmed that output came out from A and D only when it was 0x0003. (Confirmed that D output is also output through changing the path setting)
Is there any expected problem if I use 0x0003 instead of 0x0001?

Could you please explain the difference in DAC behavior depending on settings 0x0001 and 0x0003?

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Thanks,

JH

JH,

The only data value options for bits 3:0 of address 0x4D per the data sheet are 0x01 and 0x00. I do not know what 0x0003 will do as this is not a valid entry and should not be used. Also, since this device can only operate with two converters, M is always 1. So bits 15:8 of address 0x4D must be set to 0001.

So the final value of address 0x4D must be 0x0100 for this customer's setup.

Regards,

Jim