Hello,
I noticed the following in the datasheet:
Can you elaborate on the reason why the Master Clock needs to be synchronous with the SPI interface clock (SCLK)? It does not appear that the EVM is following this requirement. ADC_DIGITAL_CLK is disconnected by default and this would be the only signal that is connected to the PHI board that would permit synchronization of the SPI SCLK and Master Clock.
Thanks,
Joe
