Hi,
1. DAC 3283 datasheet says:
So it says that maximum Input data rate is 312.5 MSPS. Does this means that Max. DATACLK frequency can be 312.5 MHz.
BUT test condition says that DATACLK frequency is 625MHz. So what is max. DATACLK freq? (I am assuming here that DATACLK frequency and the clock at which 8 bit data generated for DAC is same).
2. Does the DATACLK freq should be half of the DACCLK frequency?
Hello,
The DAC3283 is a byte wide DDR interface. From plot below, it takes 2x DATACLK cycle for every completion of I/Q samples. With the I/Q rate of 312.5MSPS, this means 625MHz of DATACLK.
The relationship of DATACLK vs. DACCLK depends on the interpolation that you have selected. See below for detail.
Hi Kang Hsia
Thanks for the quick reply. this helps a lot to understand things.
So, we have DATACLK= 307.2 MHz and If we generate a square signal, we are able to generate it with high time ~ 6.5ns ( i.e. half time period = 1/(2xDATACLK). as shown in below figure:
FPGA Logic is something like:
always @(posedge fpga_clk_mmcm)begin
if(reset)begin
count <= 2'b00;
data <= 8'h00;
end
else if (count ==2'b00) begin
data <=8'h7F ;
count = count +1;
end
else if (count == 2'b10) begin
data <=8'h80;
count = count +1;
end
else count = count+1;
end
BUT if we try to generate a square signal with high time ~ 3.25ns ( half time period = 1/DATACLK). Then there is no output from DAC.
IS it because DAC need at least 2 DATACLK cycles to generate output ?
Our requirement is to generate a square signal with high time ~ 4ns.
