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[ADS41B49] REGISTER setting issue

siwon kim
Prodigy 100 points
Other Parts Discussed in Thread: ADS41B49

Hello

I am using ADS41B49 (14bit ADC but only use D2_D3 ~ D12_D13 as 12bit)

input signal(lvds) is positive so I think I should select offset binary mode

how can I set initial register?  I tried to set below map (test pattern is ramp mode) 

REG_Add

DESCRIP

register

00

RESET

02

03

High PERF

03

25

Gain & TEST_PATTERNS

C4

3D

DATA FORMAT

E0

41

LVDS Setting

40

4A

HI PERF

01

BF

OFFSET

80

the output is 

MSB 2bits (D13_D12, D10_D11) is delayed

so I changed the timing (only MSB 2bits) and the output is 

the output is normal 

I already checked post (http://e2e.ti.com/support/data_converters/high_speed_data_converters/f/68/t/230210.aspx)

but I don't  understand why MSB 2 bits (D13_D12, D10_D11) ? 

---------------------------

question  is 

1. just simple check please about register map 

2. I understand D13,D12(Pin 48,47) is toggled as test pattern but D11_D10(Pin 46,45) is also toggled? 

3. how can i select offset binary mode to use full scale (0 ~ 4096) ??

thank you 

  • 0
    TI__Genius 17310 points

    Hi,

    The register map looks okay. In ramp mode, all bits should toggle. The LSBs will toggle every clock cycle (in 12-bit, every 4 clock cycles), and each successive bit will toggle at half the rate of the previous bit. Based on the plot it looks like bit 10 is sometimes captured incorrectly and based on the spacing it may occur when bit 11 changes state. My guess is that it's still a timing issue on lane D11_D10.

    Not sure what you're asking regarding offset binary mode... In offset binary the most negative value (-1 V differential) is represented as code 0, the most positive value (+1 V differential) is represented as 4095.

    Regards,
    Matt Guibord