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ADS1278: SPI SCLK setting to read from ADS1278

Jian Chen94
Intellectual 505 points
Part Number: ADS1278
Other Parts Discussed in Thread: MSP430F2619S-HT

Hi,

I am using MSP430F2916 to read ADS1278 from 3 wire SPI interface.  From Figure 16-4, page 442 of SLAU144J (msp430 family user guide), Should I set UCCKPH 0 and UCCKPL 1 to read data from ADS1278?

The datasheet of ADS1278 shows SCLK shifts out data on the falling edge.

Thanks, Jian

  • 0
    Intellectual 505 points
    Sorry about typo, the micontroller is MSP430F2619S-HT, not MSP430F2916.
  • 0 in reply to Jian Chen94
    TI__Guru 64356 points

    Hello Jian,

    You should be able to use the CPOL = 1, CPHA = 1 configuration in your MCU. Please confirm you are meeting the SPI timing specifications on page 8 of the ADS1278 datasheet, especially the setup/hold times (i.e. tDOHD).

    *** CPOL = 0, CPHA = 0 is the correct configuration. See 1/16/17 post. ***

    Best Regards,

  • 0 in reply to Ryan Andrews
    Intellectual 505 points

    Hi Ryan,

    I am confused by the CPOL CPHA settings.  If CPOL=1, CPHA=1, (the fourth graph of figure 16-4 on page442 of SLAU144J.  The RX Sample Points are on the falling edge of SCLK(last graph of figure 16-4).  But ADS1278 shifts out data on the falling edge of SCLK.  I think the RX sample points should be on the rising edge of SCLK when no data is shifting out.   Correct me if I am wrong.

    Thanks, Jian 

  • 0 in reply to Jian Chen94
    TI__Guru 64356 points

    Hi Jian,

    I need to correct my previous post about the SCLK configuration for the ADS1278.

    You are correct that the ADS1278 shifts data out on the SCLK falling edge; therefore, the MCU should latch the data on the SCLK rising edge. However, the oversight on my part is that the ADS1278 shifts out the MSB following the falling edge of /DRDY. If SCLK begins with a falling edge, the device will shift another bit (MSB-1) and the MSB will be missed by the MCU. The correct configuration for this device is actually CPOL = 0, CPHA = 0 (MODE 0), where the rising edge occurs first and is used to latch the data. The MSB will be shifted out within 16ns (tMSBPD) of the /DRDY falling edge. The first rising edge of SCLK must occur at least one CLK period (tDS) after this /DRDY falling edge.

    Sorry for the confusion. Please let me know if you have additional questions.


    Best Regards,