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ADS7841-Q1: Requirement for DCLK

na na78
Guru 16770 points
Part Number: ADS7841-Q1
Other Parts Discussed in Thread: ADS7818

Hi

I can see the datasheet says DCLK HIGH/LOW time is 150ns (min) from the TABLE VII.

Is there any other constraint for DCLK? (such as Duty cycle)

1. Do you have maximum time of DCLK  HIGH/LOW time?

2. Is it capable to apply DCLK with 150msec high time and 1sec low time?

3. Is there specification of minimum DCLK rate (Slowest rate)?

BestRegards

  • 0
    TI__Mastermind 21847 points
    Na,

    We are looking into your request and will get back with you soon.

    Best regards,
  • 0 in reply to Art Kay
    TI__Mastermind 21685 points
    Hello,

    >>>Is there any other constraint for DCLK? (such as Duty cycle)
    Though there is no specification for the duty cycle similar devices are usually specified with a duty cycle between 40-60%.

    >>>1. Do you have maximum time of DCLK HIGH/LOW time?
    The data sheet does not specify a maximum on the DCLK HIGH/LOW time. In Figure 8 of the data sheet, effect of scaling the DCLK frequency to match the conversion rate versus maintaining the maximum possible clock frequency (fclk = 2MHz) while reducing the number of conversion per second is shown. There's significant savings in power (assuming the auto power-down mode is active) by maintaining maximum possible clock frequency. Do you know what's the minimum conversion rate (fsample-min) application needs? If you would like to scale the clock with sample rate, then use this guideline (fclk = 16 x fsample) shown in data sheet.

    >>>2. Is it capable to apply DCLK with 150msec high time and 1sec low time?

    Though there is no specification for the duty cycle similar devices are usually specified with a duty cycle between 40-60%. It's good keep duty cycle within this acceptable range.

    >>>3. Is there specification of minimum DCLK rate (Slowest rate)?
    Same as response 1 above.

    Thanks,
    Vishy
  • 0 in reply to Vishy Viswanathan
    Guru 16770 points

    Hi Vishy

    Thank you for your reply.

    Could you tell us the following questions?

    - Does fclk represent DCLK?

    > Do you know what's the minimum conversion rate (fsample-min) application needs?
    Yes. I want to know the slowest DCLK period.

    For example, the clock period of ads7818 is defined as 125nsec to 5000nsec.

    I want to know those of ads7841Q1 in the same way.


    BestRegards

  • 0 in reply to na na78
    TI__Mastermind 21685 points
    Hello,

    >>> Does fclk represent DCLK?
    fclk represents the frequency of DCLK

    >>> Do you know what's the minimum conversion rate (fsample-min) application needs?
    >>Yes. I want to know the slowest DCLK period.
    I will check internally if there is any additional information available on this. Data Sheet uses formula fclk = fsample x 16 to determine DCLK frequency to use. This is a guideline only when you want to scale clock frequency with conversion rate. Otherwise, as I said before, you get best power savings when fclk = 2MHz

    Thanks,
    Vishy
  • 0 in reply to Vishy Viswanathan
    Guru 16770 points

    Hi Vishy

    Thank you for your cooperation.
    I'll wait for the result.

    As for sampling frequency, I recognize that Fsample can be controlled with CS independent on DCLK.
    (That's why the plot with fclk=2MHz like figure 8 can be obtained.

    Is my understanding correct?

    And is the characteristics of figure 8 applied with VCC=Vref=5V?


    BestRegards

  • 0 in reply to na na78
    TI__Mastermind 21685 points
    Hello,

    >>>>As for sampling frequency, I recognize that Fsample can be controlled with CS independent on DCLK.
    (That's why the plot with fclk=2MHz like figure 8 can be obtained.
    Is my understanding correct?

    Yes, your understanding is right.

    Thanks,
    Vishy
  • 0 in reply to Vishy Viswanathan
    Guru 16770 points

    Hi Vishy

    Thank you for your reply.



    Sorry, I had added the following question. How about this? Do you have information?
    >And is the characteristics of figure 8 applied with VCC=Vref=5V?

    And I'm also looking forward to the additional information of slowest DCLK.


    BestRegards

  • 0 in reply to na na78
    TI__Mastermind 21685 points

    Hello,
    Figure 8 characteristic is for VCC = 2.7V and VREF = 2.5V
    I am still checking on the slowest DCLK. Please give me few more days.
    Thanks,
    Vishy

  • 0 in reply to Vishy Viswanathan
    TI__Mastermind 21685 points
    Hello,
    I see data sheet uses a minimum sample rate of 12.5kHz (fsample = 12.5kHz) to specify quiescent current (page 4, page 5). Using the formula fclk = 16 x fsample, this translates to a fclk of 200kHz. This translates to slowest DCLK period of 5000ns.
    Thanks,
    Vishy
  • 0 in reply to Vishy Viswanathan
    Guru 16770 points
    Hi Vishy

    Thank you for your reply.

    Sorry, the following is not clear for me yet.

    Regarding to the minimum sample rate, we will see fsample = 1KHz is the lowest from Figure 8.
    So, fclk could be led as 16KHz using fclk=16xfsample, and it leads 62usec DCLK period.
    Is 62usec not slowest ?

    BestRegards
  • 0 in reply to na na78
    TI__Mastermind 21685 points
    Hello,
    >>>Is 62usec not slowest ?
    Possbile. But I am not sure why then 1kHz was not used for specifying quiescent current but 12.5kHz. I was more conservative.
    Thanks,
    Vishy