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Hi
I can see the datasheet says DCLK HIGH/LOW time is 150ns (min) from the TABLE VII.
Is there any other constraint for DCLK? (such as Duty cycle)
1. Do you have maximum time of DCLK HIGH/LOW time?
2. Is it capable to apply DCLK with 150msec high time and 1sec low time?
3. Is there specification of minimum DCLK rate (Slowest rate)?
BestRegards
Hi Vishy
Thank you for your reply.
Could you tell us the following questions?
- Does fclk represent DCLK?
> Do you know what's the minimum conversion rate (fsample-min) application needs?
Yes. I want to know the slowest DCLK period.
For example, the clock period of ads7818 is defined as 125nsec to 5000nsec.
I want to know those of ads7841Q1 in the same way.
BestRegards
Hi Vishy
Thank you for your cooperation.
I'll wait for the result.
As for sampling frequency, I recognize that Fsample can be controlled with CS independent on DCLK.
(That's why the plot with fclk=2MHz like figure 8 can be obtained.
Is my understanding correct?
And is the characteristics of figure 8 applied with VCC=Vref=5V?
BestRegards
Hi Vishy
Thank you for your reply.
Sorry, I had added the following question. How about this? Do you have information?
>And is the characteristics of figure 8 applied with VCC=Vref=5V?
And I'm also looking forward to the additional information of slowest DCLK.
BestRegards
Hello,
Figure 8 characteristic is for VCC = 2.7V and VREF = 2.5V
I am still checking on the slowest DCLK. Please give me few more days.
Thanks,
Vishy