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DAC38J82: FIFO alarms.

Oddbjørn Norstrand
Prodigy 130 points
Part Number: DAC38J82

I have a DAC38J82 connected to a Arria 10 FPGA. On the FPGA side everything appears to be working except for an alarm about the phase compensation FIFO for JESD204B being full for the lane in use. On the DAC side I do not have analog out and the FIFO empty alarm bit is set for the lane in use (reg 0x64 bit 0). What does this indicate? What can be the causes of these alarms? How can I further investigate or resolve this problem?

  • 0
    TI__Mastermind 44240 points
    Hi user
    We have received your question. Someone will provide a more detailed response soon.
    Best regards,
    Jim B
  • 0 in reply to Jim Brinkhurst1
    TI__Guru* 91947 points

    User,

    These errors are usually caused by improper clock frequency settings. Can you send your DAC register settings? What sample rate is the DAC running at?

    What is your LMFS settings? What interpolation factor are you using? Are you using the DAC PLL? What is your K value and SYSREF frequency? What is the FPGA

    reference clock frequency?

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 130 points

    This is what I program the DAC with. The order is based on the order I found in chapter 7.5 in DAC3xJ8x Device Initialization and SYSREF Configuration (slaa696.pdf).

    #Addr: value
    0x31: 0x1000
    0x32: 0x0000
    0x33: 0x0000
    0x3B: 0x1800
    0x3C: 0x0028
    0x3D: 0x0088
    0x3E: 0x0128
    0x3F: 0x000A
    0x46: 0x0044
    0x47: 0x190A
    0x48: 0x31C3
    0x49: 0x0000
    0x4A: 0x013E
    0x4B: 0x0303
    0x4C: 0x0400
    0x4D: 0x0100
    0x4E: 0x0F6F
    0x4F: 0x1C61
    0x50: 0x0000
    0x51: 0x00FF
    0x52: 0x00FF
    0x53: 0x0000
    0x54: 0x0000
    0x55: 0x0000
    0x56: 0x0000
    0x57: 0x0000
    0x58: 0x0000
    0x59: 0x0000
    0x5A: 0x0000
    0x5B: 0x0000
    0x5C: 0x0005
    0x5E: 0x0000
    0x5F: 0x0123
    0x60: 0x4567
    0x61: 0x0111
    0x00: 0x0842
    0x01: 0x0003
    0x02: 0x00F2
    0x08: 0x0000
    0x09: 0x0000
    0x0A: 0x0000
    0x0B: 0x0000
    0x0C: 0x0400
    0x0D: 0x0400
    0x0E: 0x0400
    0x0F: 0x0400
    0x10: 0x0000
    0x11: 0x0000
    0x12: 0x0000
    0x13: 0x0000
    0x14: 0x5555
    0x15: 0x5555
    0x16: 0x4D55
    0x17: 0x0000
    0x18: 0x0000
    0x19: 0x0000
    0x4A: 0x013E
    0x24: 0x0030
    0x5C: 0x0005
    0x4A: 0x013F
    0x4A: 0x0121
    0x1A: 0x0027
    0x03: 0xF301
    0x1E: 0x1111
    0x1F: 0x9940
    0x20: 0x8088
    0x04: 0xFEFE
    0x05: 0xEF05
    0x06: 0xFEFE
    0x1B: 0x0000
    0x22: 0x1B1B
    0x23: 0x002E
    0x25: 0x6000
    0x26: 0x0000
    0x2D: 0x0001
    0x2E: 0xFFFF
    0x2F: 0x0004
    0x30: 0x0000
    0x34: 0x0000
    0x6D: 0x0000
    0x6E: 0x0000
    0x6F: 0x0000
    0x70: 0x0000
    0x71: 0x0000
    0x72: 0x0000
    0x73: 0x0000
    0x74: 0x0000
    0x75: 0x0000
    0x76: 0x0000
    0x77: 0x0000
    0x78: 0x0000
    0x79: 0x0000
    0x7A: 0x0000
    0x7B: 0x0000
    0x7C: 0x0000
    0x7D: 0x0000

    This is what I read back.
    #Addr: value
    0x00: 0x0842
    0x01: 0x0003
    0x02: 0x00f2
    0x03: 0xf301
    0x04: 0xfefe
    0x05: 0xef05
    0x06: 0xfefe
    0x07: 0x3300
    0x08: 0x0000
    0x09: 0x0000
    0x0a: 0x0000
    0x0b: 0x0000
    0x0c: 0x0400
    0x0d: 0x0400
    0x0e: 0x0400
    0x0f: 0x0400
    0x10: 0x0000
    0x11: 0x0000
    0x12: 0x0000
    0x13: 0x0000
    0x14: 0x5555
    0x15: 0x5555
    0x16: 0x4d55
    0x17: 0x0000
    0x18: 0x0000
    0x19: 0x0000
    0x1a: 0x0027
    0x1b: 0x0000
    0x1c: 0x0000
    0x1d: 0x0000
    0x1e: 0x1111
    0x1f: 0x9980
    0x20: 0x8088
    0x21: 0x0000
    0x22: 0x1b1b
    0x23: 0x002e
    0x24: 0x0030
    0x25: 0x6000
    0x26: 0x0000
    0x27: 0x0000
    0x28: 0x0003
    0x29: 0xffff
    0x2a: 0x0000
    0x2b: 0x0000
    0x2c: 0x0000
    0x2d: 0x0001
    0x2e: 0xffff
    0x2f: 0x0004
    0x30: 0x0000
    0x31: 0x1000
    0x32: 0x0000
    0x33: 0x0000
    0x34: 0x0000
    0x35: 0x0000
    0x36: 0x0000
    0x37: 0x0000
    0x38: 0x0000                             
    0x39: 0x0000                    
    0x3a: 0x0000                    
    0x3b: 0x1800                    
    0x3c: 0x0028                    
    0x3d: 0x0088                    
    0x3e: 0x0128                    
    0x3f: 0x000a                    
    0x40: 0x0000                    
    0x41: 0x0000                    
    0x42: 0x0000                    
    0x43: 0x0000                    
    0x44: 0x0000                    
    0x45: 0x0000
    0x46: 0x0044   
    0x47: 0x190a
    0x48: 0x31c3                          
    0x49: 0x0000
    0x4a: 0x0121
    0x4b: 0x0303
    0x4c: 0x0400
    0x4d: 0x0100
    0x4e: 0x0f6f
    0x4f: 0x1c61
    0x50: 0x0000
    0x51: 0x00ff
    0x52: 0x00ff
    0x53: 0x0000
    0x54: 0x0000
    0x55: 0x0000
    0x56: 0x0000
    0x57: 0x0000
    0x58: 0x0000
    0x59: 0x0000
    0x5a: 0x0000
    0x5b: 0x0000
    0x5c: 0x0005
    0x5d: 0x0000
    0x5e: 0x0000
    0x5f: 0x0123
    0x60: 0x4567
    0x61: 0x0111
    0x62: 0x0000
    0x63: 0x0000
    0x64: 0x0001
    0x65: 0xfd0f
    0x66: 0xff0c
    0x67: 0xff0a
    0x68: 0xc307
    0x69: 0xfe0b
    0x6a: 0x660e
    0x6b: 0xde0a
    0x6c: 0x0007
    0x6d: 0x00e0
    0x6e: 0x0000
    0x6f: 0x0000
    0x70: 0x0000
    0x71: 0x0000
    0x72: 0x0000
    0x73: 0x0000
    0x74: 0x0000
    0x75: 0x0000
    0x76: 0x0000
    0x77: 0x0000
    0x78: 0x0000
    0x79: 0x0000
    0x7a: 0x0000
    0x7b: 0x0000
    0x7c: 0x0000
    0x7d: 0x0000
    0x7e: 0x0000
    0x7f: 0x800a

    The DAC sample rate is 2.4GHz. L=1, M=2, F=4, S=1. Interpolation factor is 16. I am not using the DAC PLL. K is 5. Sysref is gapped periodic of 16 pulses with a frequency of 15MHz. The FPGA reference clock frequency is 150MHz.

  • 0 in reply to Oddbjørn Norstrand
    TI__Guru* 91947 points

    User,

    There appears to be many register  settings that may be incorrect. If you are  using RX0 as the input for the one lane of the DAC, please try the settings in the register file attached. This has all of your settings taken into account and was tested with our EVM's. Make sure you do a board reset after power and clocks are provided, load the register settings, then have the FPGA start transmitting data, then issue a DAC JESD Core reset then trigger the SYSREF pulses.

    Regards,

    Jim

    2400_Fs_124_dspNor.cfgDAC38J82_LMF_124_16x_int.pptx

     

  • 0 in reply to jim s
    Prodigy 130 points
    Thank you. With your register values and some changes to the sender I now have an analog output. However the DAC is not working in the mode I want it so some manual merging of your settings and mine settings are required. Here are some questions and comments on the register settings.

    #Addr: mine yours
    0x00: 0x0842 0x818
    Bit 1: We would like to have the inverse sinc filter for DAC A.
    Bit 3,4: I do not really care about alarm since it is not routed to anything on my board.
    Bit6: This one I do not fully understand. Do this one need to be set to 1 to enable the summing of the outputs of the full mixer or is this something else?

    0x01: 0x0003 0x003
    Agree.

    0x02: 0x00F2 0x2002
    Bit 4: We are going to use the full NCO.
    Bit 5: We want the extra 6dB gain.
    Bit 6: We want to use the mixer.
    Bit 7: Our board uses a 4-wire interface.
    Bit 13: We will turn this on.

    0x03: 0xF301 0xA300
    Bit0: OK, we are driving the TXENABLE pin high so we should not need to set this bit high.
    Bit15..12: We would like to have maximum output power.

    0x04: 0xFEFE 0xF7F7
    If I am to only use one lane must that be lane 3?

    0x05: 0xEF05 0xFF07
    Bit1: Why would we not want the SYSREF setup/hold alarm?
    Bit12: Why would we not want the SYSREF errors for link0?

    0x06: 0xFEFE 0xFFFF
    Why are you masking the alarms for all lanes? Am I misunderstanding the polarity of the masks? Does 0 means that we will see the alarms and 1 that we will not see them?

    0x07: None, 0x3100
    This register looks like a read only register to me, why are we writing to it?

    0x08: 0x0000 0x0000
    Agree.

    0x09: 0x0000 0x0000
    Agree.

    0x0A: 0x0000 0x0000
    Agree.

    0x0B: 0x0000 0x0000
    Agree.

    0x0C: 0x0400 0x0400
    Agree.

    0x0D: 0x0400 0x0400
    Agree.

    0x0E: 0x0400 0x0400
    Agree.

    0x0F: 0x0400 0x0400
    Agree.

    0x10: 0x0000 0x0000
    Agree.

    0x11: 0x0000 0x0000
    Agree.

    0x12: 0x0000 0x0000
    Agree.

    0x13: 0x0000 0x0000
    Agree.

    0x14: 0x5555 0x0000
    We want the NCO frequency to be 725MHz.

    0x15: 0x5555 0x0000
    We want the NCO frequency to be 725MHz.

    0x16: 0x4D55 0x0000
    We want the NCO frequency to be 725MHz.

    0x17: 0x0000 0x0000
    Agree.

    0x18: 0x0000 0x0000
    Agree.

    0x19: 0x0000 0x0000
    Agree.

    0x1A: 0x0027 0x0023
    Bit2: We are not using the output of DACB so we put it to sleep. Will that affect the output of DAC A or anything else?

    0x1B: 0x0000 0x0000
    Agree.

    0x1E: 0x1111 0x9999
    I can enable sif_sync here but QMC is not intended to be used and disabled in reg 0x00. Is sync required to HW that is not in use?

    0x1F: 0x9940 0x9980
    Bit7..4: I can try to change the syncsel_nco source.

    0x20: 0x8088 0x8008
    Bit7..4: I can try to remove all sync sources for PAP.

    0x22, 0x1B1B 0x1B1B
    Agree.

    0x23: 0x002E 0x01FF
    I can allow all things to go to sleep, I had just disabled the things I now will be used to be sure it was not sleeping.

    0x24: 0x0030 0x0020
    I can try to change which sysref pulse is used. I have already tried different settings here. Based on the DAC3xJ8x Device Initialization and SYSREF Configuration (slaa696.pdf) using the second pulse to initialize the clock divider and the third to initialize the JESD204B is a good approach, but first and second can also be used it says.

    0x25: 0x6000 0x6000
    Agree.

    0x26: 0x0000 0x0000
    Agree.

    0x2D: 0x0001 0x0001
    Agree.

    0x2E: 0xFFFF 0xFFFF
    Agree.

    0x2F: 0x0004 0x0004
    Agree.

    0x30: 0x0000 0x0000
    Agree.

    0x31: 0x1000 0x1000
    Agree.

    0x32: 0x0000 0x0000
    Agree.

    0x33: 0x0000 0x0000
    Agree

    0x34: 0x0000 0x0000
    Agree.

    0x3B: 0x1800 0x1800
    Agree.

    0x3C: 0x0028 0x0028
    Agree.

    0x3D: 0x0088 0x0088
    Agree.

    0x3E: 0x0128 0x0128
    Agree.

    0x3F: 0x000A 0x0000
    Bit1,3: Lanes 1 and 3 are inverted on our board. But only lane 0 is intended to be used for this configuration.

    0x46: 0x0044 0x0082
    I can try changing the IDs. My plan was to use RX0, SERDES0, JESD0, ID0 ... Why will that not work even though that is the default register values?

    0x47: 0x190A 0x19C8
    I can try changing the IDs.

    x0x48: 0x31C3 0x3143
    I can try changing the IDs.

    0x49: 0x0000 0x0000
    Agree.

    0x4A: 0x013E,0x013F,0x0121 0x0121
    Agree.

    0x4B: 0x0303 0x0303
    Agree.

    0x4C: 0x0400 0x0400
    Agree.

    0x4D: 0x0100 0x0100
    Agree.

    0x4E: 0x0F6F 0x0F0F
    Bit5: The sender has scrambler turned on. I can try without scrambler enabled on the sender and disable it here.
    Bit6: The sender has HD turned on. HD makes little difference, I can turn it off on the sender and disable it here.

    0x4F: 0x1C61 0x1C61
    Agree.

    0x50: 0x000 0x0000
    Agree.

    0x51: 0x00FF 0x00DC
    I can change what will cause a sync request.

    0x52: 0x00FF 0x00FF
    Agree.

    0x53: 0x0000 0x0000
    Agree.

    0x54: 0x0000 0x00FC
    Bit7..0: Why would I want a error for link1 which I am not using to be able to cause a sync request?

    0x55: 0x0000 0x00FF
    Bit7..0: I can change these bits, but I do not care for errors for link1 since I do not use it.

    0x56: 0x0000 0x0000
    Agree.

    0x57: 0x0000 0x00FF
    Bit7..0: Why would I want a error for link2 which I am not using to be able to cause a sync request?

    0x58: 0x0000 0x00FF
    Bit7..0: I can change these bits, but I do not care for errors for link2 since I do not use it.

    0x59: 0x0000 0x0000
    Agree.

    0x5A: 0x0000 0x00FF
    Bit7..0: Why would I want a error for link3 which I am not using to be able to cause a sync request?

    0x5B: 0x0000 0x00FF
    Bit7..0: I can change these bits, but I do not care for errors for link3 since I do not use it.

    0x5C: 0x0005 0x1133
    Bit2..0: I can try to change which sysref pulse is used. I have already tried different settings here. Based on the DAC3xJ8x Device Initialization and SYSREF Configuration (slaa696.pdf) using the second pulse to initialize the clock divider and the third to initialize the JESD204B is a good approach, but first and second can also be used it says.
    Bit6..4: Do I need SYSREF for link1?
    Bit10..8: Do I need SYSREF for link2?
    Bit14..12: Do I need SYSREF for link3?

    0x5E: 0x0000 0x0000
    Agree.

    0x5F: 0x0123 0x0214
    I can try changing the mapping. My plan was to use RX0, SERDES0, JESD0, ID0 ... Why will that not work even though that is the default register values?

    0x60: 0x4567 0x5764
    I can try changing the mapping.

    0x61: 0x0111 0x0211
    Bit11..8: Since I do not use link1 I set it to link0. I can change it to link1 and see it that makes any difference.

    0x64: None 0x0001
    How does the write to clear work? Will the write of any value clear all the bits or will it clear the bits written high or low? I write 0x0000 to the write to clear registers to clear the alarms.

    0x65: None 0x0001
    Is this for Lane1? The data sheet says Lane0/Lane1.

    0x66: None 0x0001
    Is this for Lane2? The data sheet says Lane0/Lane2.

    0x67: None 0x0001
    Is this for Lane3? The data sheet says Lane0/Lane3.

    0x68: None 0x7709
    Is this for Lane4? The data sheet says Lane0/Lane4. Why is the value different than for the value written to 0x64 -- 0x67?

    0x69: None 0x0000
    Is this for Lane5? The data sheet says Lane0/Lane5. Why is the value different than for the value written to 0x64 -- 0x68?

    0x6A: None 0x0000
    Is this for Lane6? The data sheet says Lane0/Lane6.

    0x6B: None 0xBD07
    Is this for Lane7? The data sheet says Lane0/Lane7. Why is the value different than for the value written to 0x64 -- 0x68?

    0x6C: None 0x0007
    OK.

    0x6D: 0x0000 0x0090
    Why are we writing to what appears to be a read only register? How are these alarms cleared? Is it perhaps a write to clear register?

    0x6E: 0x0000 0x0000
    Agree.

    0x6F: 0x0000 0x0000
    Agree.

    0x70: 0x0000 0x0000
    Agree.

    0x71: 0x0000 0x0000
    Agree.

    0x72: 0x0000 0x0000
    Agree.

    0x73: 0x0000 0x0000
    Agree.

    0x74: 0x0000 0x0000
    Agree.

    0x75: 0x0000 0x0000
    Agree.

    0x76: 0x0000 0x0000
    Agree.

    0x77: 0x0000 0x0000
    Agree.

    0x78: 0x0000 0x0000
    Agree.

    0x79: 0x0000 0x0000
    Agree.

    0x7A: 0x0000 0x0000
    Agree.

    0x7B: 0x0000 0x0000
    Agree.

    0x7C: 0x0000 0x0000
    Agree.

    0x7D: 0x0000 0x0000
    Agree.
  • 0 in reply to Oddbjørn Norstrand
    TI__Guru* 91947 points

    2400_Fs_124_NCO_725_dspNor.cfgUser,

    I went back to my original config file and made all the changes to reflect your settings. Other than the inverse polarity, everything you had works fine with our system except for address 0x4E. This has to have HD = 0 on both the transmitter and receiver for this mode to work with one lane. You can use the scrambler but make sure the FPGA is set to this as well. We normally have this turned off. There was a lot of settings in my file that were setup to the default value or some setting that did not make since due to the GUI, which I did not create. Please take a look at the new config file attached.

    Regards,

    Jim