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DAC38RF82: strange behavior of DAC B

haopeng han
Expert 1120 points
Part Number: DAC38RF82
Other Parts Discussed in Thread: , LMK04828

Hi,
we are evaluating DAC38RF82 with DAC38RF82EVM+ZCU102. The only hardware modification I made is soldering R10 onto the EVM board to use the single-ended SYNC~ signal. We use the Xilinx JESD204 IP core to talk to the DAC.
Attached our EVM .cfg file. We use clock mode 4: on-board VCXO clock mode. LMK PLL VCO1 set to 3072MHz, FPGA device clock=192MHz, DAC device clock=122.88MHz, sysref=19.2MHz, Fdac = 6144Msps, Linerate=7680M, DAC on chip PLL mode, Dual DAC, single link, real, LMFSHd = 82121,4x Interpolation, DAC PLL settings M = 25, N = 2. We use the same settings for both DAC A and B. It seems that DAC B is not working properly.

In the FPGA we first set DAC A and DAC B to the same sine wave data flow. As showed in Fig1, we can get correct output (24MHz) from DAC A, but weird signal out from DAC B. Both DACs generate stable signals.

Then we changed the sine lookup table step size to 2 for DAC A to output 48MHz, and set DAC B for a 192MHz square wave. Fig2 shows what we got. The signals seem to be correct (at least for the frequency). But they are not stable, the signals stop frequently as showed in Fig3.

Attached also the verilog file for signal generation. I also checked the FPGA pin assignment, they should be right.

Could you please help us with this case? Thanks in advance!

Best,

Han

files.7z

Fig1:

Fig2:

Fig3:

  • 0
    TI__Guru* 91947 points

    Han,

    Did you try generating just a NCO output tone for CHB to see if this was valid? Also, try swapping the 4 serdes lanes used by CHA with CHB to see if the problem is the FPGA or DAC. Can you send screen shots of the DAC GUI with the settings you are loading? The GUI does not allow the config file to refresh the screen settings and it would take me some time to decode all of the register settings. 

    Regards,

    Jim

  • 0 in reply to jim s
    Expert 1120 points

    Thanks Jim for your support!

    The NCO works fine with CHB. Attached our test procedures and GUI settings. Please help to check it. Thank you! test.docx

  • 0 in reply to haopeng han
    TI__Guru* 91947 points

    Han,

    I think your upper 4 lanes are mapped wrong when looking  at your screen shot of the GUI.  Please try the settings shown in the attached document. What is the reference clock frequency you are sending to the EVM?

    Regards,

    Jim

    Serdes and Lane Config.pptx

  • 0 in reply to jim s
    Expert 1120 points

    Hi Jim,

    I tried with your setting, but it does not work. I attached a picture of the signals and an explanation of the physical connections between two boards.

    Reference clock frequency to the EVM? You mean on SMA J4? J4 is not connected in my setting, I use CMODE4, only the on board 122.88MHz TCXO reference. The LMK04828 settings were copied from your post.

    For the FPGA, I am using the LMK generated 192MHz for both SerDes clock and device clock.

    Thanks & Best,

    Han

    0743.test0404.docx

  • 0 in reply to haopeng han
    TI__Guru* 91947 points

    lane mapping_DAC38RF8x_EVM.xlsxHan,

    Your notes are very confusing to me. You should have TX0 - TX7 for DAC RX0-RX7. But I only see TX0-TX3 and these are repeated. Please take a look at the attached table and a new column that shows how the lane ID's are mapped to the serdes going to the DAC inputs with your firmware.

    Regards,

    Jim

     

  • 0 in reply to jim s
    Expert 1120 points

    Hi Jim,

    sorry about causing the confusion, because RX4-7 are connected to another bank in the FPGA, they have the same pin names, please see my notes.

    I think the lane id mapping in your table corresponds to another board, not the ZCU102. I send you the related schemetic.

    It's really strange that the data flows in one link, with the same settings CHA works fine but CHB is not working. I attached our design. Is it possilbe that you or your colleague try it with DAC28RF82EVM+ZCU102? That would be much appreciated!!


    In the meantime, I will try

    1, LMF=811

    2, two DACs, two JESD204 links

    3, change the waveform to hopefully find a error pattern

    Thank you!

    Best,

    Han

  • 0 in reply to haopeng han
    TI__Guru* 91947 points

    Han,

    Do you still need help with this issue?

    Regards,

    Jim

  • 0 in reply to jim s
    Expert 1120 points
    Hi Jim,
    We can now output waveforms from both ChA & ChB. But only with the HPC1 FMC interface.
    The issue now is ChA and ChB are not phace aligned when use this setup to generate two 300MHz sine waves. We put exactly the same waveforms to ChA and ChB. But there is a phase difference between the two channels. What could be wrong?
    Thanks,
    Han
  • 0 in reply to haopeng han
    TI__Guru* 91947 points

    Han,

    The CHB outputs from the DAC are swapped with respect to CHA to make the routing easier on the EVM. This will cause a difference in phase with the same data. In the GUI under the two Digital tabs, there is an option to invert the DAC outputs. Give this a try.

    Regards,

    Jim