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Dear,
I have ADS5263 in my design，schematic as below:
CLKP is a single ended 12.5M 3.3V CMOS clock.
When I debugged the board, I found the ADCLK and LCLK is not related to CLKP.
The ADCLK and LCLK have the same output as I remove R45 and keep the CLKP Pin floating.
It seems the PLL in ADS5263 is not locked and behave like there is no CLKP input.
CLKP wave: 12.5MHz, 3.3V CMOS
ADCLKP: about 300Hz clock, duty cycle is not stable
LLCKP: about 4kHz, duty cycle is not stable
