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DM3730 18bit LCD Parallel to 3-lane LVDS LCD Inrterface

Other Parts Discussed in Thread: DM3730

Dear members 

I am in charge of HW , and I am checking LCD 18bit interface for 3-Lane LVDS LCD Module.

[Case 1] 

H/W was designed for 4-lanes LVDS LCD Module using SN65LVDS93ADGGR.

I think that HW can't support without changing DSS_DATA BUS for 18 bit. ( with lefting open  Y3P & Y3M of SN65LVDS93ADGGR)

DISPC_CONTROL Register can be set 18-bit mode. 

Can LVDS display normally under 18-bit mode setting(by DISPC_CONTROL)/Open pin(Y3P/Y3M) conditions? 

[CASE2] 

I will change the schematic as below(or attached) 

I want to know whether DSS_BUS mapping  is correct for 18bit RGB or not . 

Is this solution correct? 

If yes, Could you inform registers which will be changed for 18-bit interface? 

7635.DM3730_LCD Interface_20130613.xlsx

Thanks 

  • Hi ES KIM,

    The schematic on Case2 solution seems correct.

    About configuration of the DISPC registers read section 7.6.5.1.4.2 Configure DISPC Timing, Window, and Color in the TRM. Pay attention on the DISPC_CONTROL[9:8] bits TFTDATALINES set to 0x2.

    BR

    Tsvetolin Shulev

  • Dear TI 

    Thank you for your reply.

    I have some question about 18-bit interface. 

    Q1) According to DM3730 Technical note, I understood that 18-bit Interface can't use look-up table and OSD Function. 

          12/16/24 bits I/F can use loo-up table. 

          Is that correct? 

         What is the function that DM3730 can't support under 18-bit interface conditions? ( as compared to 24bit and 16 bit interface) 

        

    Q2) According to logic-PD as attached 

    16-bit SOM Hardware Interface to 18-bit LCD Panel
    Before the OS display driver can work, the microprocessor LCD controller must be connected correctly to the LCD color signals. In this example, we connect a 16-bit CPU hardware interface to an 18-bit LCD panel. The advantage of using 16-bit is that the software driver support is already available and does not cause the same loss of performance that may occur when supporting 18-bit display panels due to extra data being fetched across the memory bus. The extra low-order bits for red and blue on the LCD panel are simply driven with copies of the high order bits.

    We will use the schematic as attached. 

    Is that correct? 

     3225.1020853B_AN502_LogicPD_DevKit_LVDS_Integration (1).pdf