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SN65CML100: What should be VBB value when termination IC has 3.3 Voltage reference

Part Number: SN65CML100


Trying to use SN65CML100 in my design.

Using Lattice FPGA to drive true LVDS signals and need to convert them to HDMI physical layer compatible (CML)

On terminal side Chip which converts from HDMI (TMDS) to TTL logic for my RGB display, here is the snapshot of AC specs

I wanted to run through TI experts and understand if my design for SN65CML100 is okay ?

have to not completely understood how to set output CML Voltage bias required by HDMI to TTL IC on SN65CML100

Can you please help ?