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Hi, TI Team
I have some questions about TMDS181 with your help.I design one board that it supports one HMDI output (source) port and one HMDI input (sink) port. The HDMI signal connect between FPGA and HDMI connector.These HDMI siganls use TMDS181 retimer chips .
If FPGA load the software of input HDMI and the HDMI input port connect to computer with HDMI cable,the HDMI can linkup;
If FPGA load the software of output HDMI and the HDMI input port connect to the display of hdmi with HDMI cable,the HDMI can linkup;
however,If input HDMI port of one board connect to output HDMI port of another board with HDMI cable,the HDMI link down. The hdp (source and sink) can snoop,but the input side of HDMI dispaly that
the RX mode is DVI.
Hardware configuration:
1.choose pin strap mode;
2、pin17 SIG_ EN 64.9k up to gnd
3、PIN 20 PRE_ SEL floating
4、PIN36 TX_ TERM_ CTL floating
Can you give mie some ideas to solve this problem?
Hi,
1. Please check the pullup on the DDC for the source and sink side. The source side needs to be 2k while the sink side needs to 47k
2. On the sink side, does the FPGA load up its EDID info, and then drive its HPD high?
3. Do you have a I2C protocol analyzer that you can use to snoop the DDC bus and verify the data on the DDC bus matches with the sink's EDID?
4. For TMDS181, please make sure SCL_SRC and SDA_SRC are tied to ground when not being used.
Thanks
David