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Hello,
I am currently working on implementing the TMDS181RGZT HDMI Retimer to one of our designs and we're coming across some issues. At first, the system was performing well and the video quality at 4K, which was low before the retimer was implemented, was clear. However, after some time, we were not getting any output from the retimer and the system stopped working. We have checked the voltage rails VCC and VDD and both came out at 3.3V and 1.2V, respectively. We are running the retimer through pin strap mode and we believe we have all of the pin straps set up correctly. We did notice one thing, which we want to address to TI:
We are using a voltage supervisor to turn on the power rails of the retimer. Vcc would come up first, Vdd would come up second 10 ms later, and OE would go high 10 ms after Vdd comes up. The datasheet power up requirements have Vdd/Vcc coming up first, followed up by Vcc/Vdd with a max wait of 200 us. OE follows up 100 us later. The ambiguity sort of comes from section 8.3.2 Operation Timing, where it says if OE is held low until VDD and VCC become stable, there is no rail sequence requirement. Does having 10 ms delay between the two rails and the OE cause issues on the chip itself? We have tried running a test with Vdd and Vcc coming up at the same time and then having OE come up, but that didn't work either. Any help would be appreciated.
Please let me know if you need the pin strap configuration in case that would help you out in any sort of way.
Thanks