• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 128 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TLK10022: CLKOUT_A/B outputs relation with HSTX_A/B outputs

Reza Anvari
Prodigy 60 points
Part Number: TLK10022

Hello,

I have  a couple of 7.2Gbps aggregated data streams sent out at TLK10022 HSTX_A/B_P/N outputs and received by Xilinx FPGA at MGTHRXP/N inputs.

Regarding the FPGA RXDATA CLK one option is to use the recovered CLK from the RXDATA inside the FPGA and another would be to feed an RXCLK as the REF CLK to the FPGA to have a better RX CLK quality especially from jitter stand point.

I am using a single REF CLK to drive both TLK10022 A/B channels and use only the aggregator portion of TLK10022 (TX side).

TLK10022 has CLKOUT_A/B_P/N outputs and according to the datasheet it could be driven by HS_RXBCLK_A/B (not used in my case) or VCO_CLK_A/B_DIV2.

Q1) VCO_CLK_A/B_DIV2 and its relation with HSTXA/B_P/N output data stream at 7.2Gbps, regarding the frequency, delay between CLK/DATA, etc.

Q2) Since I don't use the HSRX_A/B_P/N RX side what is the TI recommendation for the unused RX CML inputs and overall RX section?

Regards,

Reza

  • 0
    TI__Mastermind 19225 points

    Hi,

    1. VCO_CLOCK_AB_div2 is a clock signal that is also recovered from the input data. Its frequency is equal to the VCO frequency divided by 2. It should be synchronized to the data. The user gets to configure this VCO frequency via the choosing of the PLL multiplier frequency. I unfortunately do not have delay data for it.
    2. 50 ohm termination to GND is ok for unused high-speed I/O pins

    Thanks,

    Rodrigo Natal

  • 0 in reply to Rodrigo Natal
    Prodigy 60 points

    Hi Rodrigo,

    Thank you for the response, two more quick questions.

    Q1) Is it correct to say, since I only use the data aggregator section of LNK10022 on both channels A/B, there won't be any signal sent out on LNK10022 CLKOUT_A/B outputs?

    Q2) I use LNK10022 as aggregator to aggregate a couple of "4 low speed streams each at 1.8Gbps" and make "faster data streams at 7.2Gbps". 

    Does the REFCLK0P/N that I feed into LNK10022 (300MHz in my case) needs to be in sync with the low speed data that I feed into INA[3:0]P/N & INB[3:0]P/N at low speed inputs at 1.8Gbps? According to datasheet I don't see such a requirement though.

    Regards,

    Reza

  • +1 in reply to Reza Anvari
    TI__Mastermind 19225 points

    Q1) Is it correct to say, since I only use the data aggregator section of LNK10022 on both channels A/B, there won't be any signal sent out on LNK10022 CLKOUT_A/B outputs?

    • See below description from the datasheet. This output is enabled by default.

    Channel A/B Output Clock. By default, this output is enabled and outputs the high speed side Channel A
    recovered byte clock (high speed line rate divided by 20). Optionally it can be configured to output the VCO
    clock divided by 2. Additional MDIO-selectable divide ratios of 1, 2, 4, 5, 8, 10, 16, 20, and 25 are available.

    Q2) I use LNK10022 as aggregator to aggregate a couple of "4 low speed streams each at 1.8Gbps" and make "faster data streams at 7.2Gbps". Does the REFCLK0P/N that I feed into LNK10022 (300MHz in my case) needs to be in sync with the low speed data that I feed into INA[3:0]P/N & INB[3:0]P/N at low speed inputs at 1.8Gbps? According to datasheet I don't see such a requirement though.

    • No, it does not

    Thanks,

    Rodrigo Natal