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DS90UB933-Q1: DS90UB933 for Triggered sensor mode

fabio ortolano
Intellectual 330 points
Part Number: DS90UB933-Q1

Hello

we are developing a TX/RX system based on DS90UB933 and DS90UB934 and using ONSEMI (ex Aptina) CMOS sensors like AR0134. The sensor works with an output clock of 48MHz. 

In continous mode, when the output clock is always drived on the sensor output, the system works weel. The frames are correctly transfered on the other side and captured.

When we move to triggered mode and send a trigger to sensor every "X"ms, the clock is not alwayd drived on the output of the sensor. Usally, there are some "blank" lines (about 10) out of the sensor before the frame valid, so there is a huge number of pixel clocks before the frame starts. What we facing is that the receiver fails to receive correctly the frame. Monitoring the LOCK or PASS pin shows a strange behaviour, like the receiver tries to syntonize with the clock but fails in the middle of the frame. Another thing is that the PASS goes high a lot of line valid AFTER the frame valid and goes low with the last line (stop of the clock). It means that the receiver takes a lot of time to syncronize. A tipical line is about 1280pixels so is quite long.

What can we do for working in triggered mode with this devices?

Thanks

  • 0
    TI__Guru* 98955 points

    Hello Fabio,

    These devices are not designed to tolerate a non-continuous clock input because the clock is used to both drive the serial link clock and to capture the data at the serializer. So you need to ensure that the PCLK input to 933 is continuous 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Intellectual 330 points

    Hello Casey

    ok so you tell me that a always present clock must be drived to the serializer. But, what about the clock use? What I mean, the 933 could be drived with a fixed clock on GPIO3/CLKIN with an higher clock rather then th PIXCLOK? And on receiver, what I will facing on CLOCKOUT?

    In my case, the sensor outputs at 60MHz. I wondering if I could use a 80MHz to GPIO3/CLKIN on serializer but on the receiver side I need to reconstruct the 60MHz of course.

    Thanks

  • 0 in reply to fabio ortolano
    TI__Guru* 98955 points

    Hello Fabio,

    933 has two different clock modes - one where the FPD clock is sourced from the PCLK input directly from the imager, and one where the CLKIN pin is connected to an external OSC and then the FPD side is sourced from that external clock input instead. In external CLKIN mode, the CLKIN and PCLK from the imager must maintain a specific ratio of frequency which is described in section 7.4.1 of the datasheet. 

    On the 934 side, the PCLK output will always match the PCLK input frequency from the imager. 

    Best Regards,

    Casey