Please explain the behavior of the CONGIG PINS internal PULL-ups/downs and the timing of the sampling of these pins.
The statement below from the datasheet seems to imply that the internal PULLS on the config pins would be ACTIVE when the EN pin is LOW...and that they get disabled AFTER the EN transitions low-high
In order to conserve power, the TUSB1002 disables 4-level input’s internal pull-up/pull down resistors after the state of 4-level pins have been sampled on rising edge of EN. A change of state for any four level input pin is not applied to USB1002 until after EN pin transitions from low to high.
However, that is not what I am seeing on the board. After I turn on the power, with the CFG pins FLOATING, I measure ZERO VOLTS on these pins, even though they are in F and R states.
What I see on the scope, is that the PULLS seem to be turned ON approx 10uS AFTER the rising edge of the EN, and then turned OFF about 470us later.
I did not see anything in the DS that alludes to the fact that the INTERNAL PULLs are pretty much always OFF , and they get turned ON when EN goes high, sampled, and then turned OFF.
To make things even more confusing, Figure 2 in the datasheet, indicates that the CFG PINS values need to be held steady for CFG_HD = 500us after EN goes high. But the chip itself turns OFF the internal pulls after less than 500us. Perhaps the meaning of tcfg_hd is different than "hold the data on the input for HOLD time after the clock"?
When exactly are these CFG pins samples? I can't possibly see how they could be sampled on rising edge of EN when apparently the PULLS are not even ON when EN goes high.
Do the below waveforms look like what I should expect to see in normal operation?
GREEN trace = EN
MAGENTA, CYAN traces = CFG pins (one in F state and the other in R)
