DP83867IS: Wrong phy address setting with strap pins

Part Number: DP83867IS

Hi all

Would you mind if we ask DP83867IS?

This thread is relation to following forum.
https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1048227/dp83867is-phy-address-setting-with-strap-pins

"Please update when scope captures are available of bad reset."
"This will help determine what exactly is going one when the PHY straps into a different address during that 1 out of 400 reoccurrence. "

->The customer could capture bad condition and normal condition. Could you refer to the following file?

20211220_DP83867.pdf

<Question1>
There is no difference between no problem case and problem case.
-problem case : 296mV
-no problem case : 288mV
The voltage is within from  0.140 × VDDIO to 0.191 × VDDIO at both case.

Just before fixed of strap setting, it seems that pin's voltage raises.
Why does the voltage raise? Because of SGMII interface, there is no packet.
And these pins have only Mode2 resistor.
Because of transition timing(from strap pin to clkout pin), does the voltage raise at the moment?

<Question2>
When does the device operate sampling of strap setting?

<Question3>
If you have EVM, could you confirm with EVM?


Kind regards,

Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto

    Thank you for the Query.

    Did you previously share the schematics and was the schematics reviewed. 

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for your reply!
    We sent you the shematics using private message.

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San, 

    Thank you for the schematics.

    I will review and provide my inputs in the next couple of days.

    Regards,

    Sreenivasa

  • Hello Hirotaka Matsumoto-San, 

    I am reviewing the schematics. 

    As i review the schematics, can you please increase the GEPHY_RSTn reset time by an additional 500us and test.

    Thank you for the help.

    Regards,

    Sreenivasa

  • Hello Hirotaka Matsumoto-San, 

    Can you please share the CN3 datasheet or specs. I am not able to find the same.

    Regards,

    Sreenivasa

  • Kallikuppa san


    Thank you for your reply.

    As i review the schematics, can you please increase the GEPHY_RSTn reset time by an additional 500us and test.
    ->We would like to confirm it.
       Does it mean T4 timing? or T1?

      Our customer's case is Figure2 Reset Timing.

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San, 

    Thank you for the reply and this is correct.

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for your reply.

    "As i review the schematics, can you please increase the GEPHY_RSTn reset time by an additional 500us"
    ->Our customer's reset timing is XXsec order, so it is enough.

    And, we confirm CN3 now, we will feed back later.

    We assume that this problem is relation to sampling timing, if you have some opinions, please let us know.

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San, 

    Thank you for the reply.

    We assume that this problem is relation to sampling timing, if you have some opinions, please let us know.

    You are right. This is related to the sampling time of the straps.

    Our customer's reset timing is XXsec order, so it is enough.

     Our customer's case is Figure2 Reset Timing -  is the customer holding the device in reset for XX sec time. This should be fine.

    Did customer perform some tests with this reset timing ?

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for your reply.

    The customer operates like as Figure2 Reset Timing.

    Test : Reset_N Low(XXsec level)  -> Reset_N High -> MDC toggling -> Confirm of address
    Repeat of above Test.

    Could you refer to the following forum?
    e2e.ti.com/.../dp83867is-phy-address-setting-with-strap-pins
    It is 1 out of 400 reoccurrence problem.

    The strap voltage is the same between NG case and OK case. 
    Therefore, it is relation to samling timing at the device. We would like to know when the device operates sampling.

    We send you the CN3 spec using private message.

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San, 

    Thank you for the input.

    It is related to the discharge timing. The reset  timing may be in the boundary. Please suggest customer to increase the reset time and check.

    Regards,

    Srenivasa

  • Kallikuppa san

    Thank you for your reply.

    It is related to the discharge timing. The reset  timing may be in the boundary. Please suggest customer to increase the reset time and check.
    ->Furthermore, the customer checked with 10s interval to discharge capacitance charge.(for cold start)
       However, the result was the same.

       Therefore, we would like to know when the device operates sampling.


    Kind regards,

    Hirotaka Matsumoto



  • Hello Hirotaka Matsumoto

    Thank you for the reply.

    ->Furthermore, the customer checked with 10s interval to discharge capacitance charge.(for cold start)
       However, the result was the same.

    Did customer hold the device in reset for 10 seconds ?

    Figure 2. Reset Timing, please refer to T2 for the hardware strap latching.

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for your reply.

    10sec means T4 on Figure2. We think it is enough discharge time.
    If the RESET is Low, we think it is the cold start.
    In addition to it, it seeems that the voltage of straps is the static like as follows file;

    20211220_DP83867.pdf

    We might not understand your mention correctly.
    Could you let us know which of T2 or T4 on Figure2 should increase?

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto

    Thank you for the reply.

    RESET pulse width is T2. T4 is the latching time. 

    Is is customer testing - by powering off and powering on the device, performing Reset as in figure 2 and then reading ?

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for your reply.

    Is is customer testing - by powering off and powering on the device, performing Reset as in figure 2 and then reading ?
    ->No, they are testing with power on(keeping VDD on) like as Figure 2 Reset timing, they operated Reset toggling.
       T4(RESET pulse width) is more than XXsec.
       Then, they keeps sequence which writes on the datasheet. 
       In addition to it, it seeems that the voltage of straps is the static.
       

    Even thought the voltage of straps is the same, we don't understand why the address setting is mis-reading with 1 out of 400.

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto

    Thank you for the detailed explanation.

    If the power is not cycled, T4 can be a few ms and not xx seconds.

    Did customer try increasing the T2 time to before reading the register ?

    Is there no communication happening on SGMII interface during reset ?

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for your reply.

    Did customer try increasing the T2 time to before reading the register ?
    ->On the following forum, Gerome san mentioned "Regarding your captures, this looks fine."
       e2e.ti.com/.../dp83867is-phy-address-setting-with-strap-pins
    "Regarding your captures, this looks fine. MDC should toggle 200ms minimum from when all supplies are ramped up and if coming from reset, 200us from  when reset is high."
       Now our customer's T2=400us, on the datasheet, it seems that it is enough, however should we increase T2 time from400us to 1ms?

    Is there no communication happening on SGMII interface during reset ?
    ->Yes, it is no communication no cable connceting, and RX_D0 is SGMII_COP, it is not data out pin.

    Kind regards,

    Hirotaka Matsumoto  

  • Hello Hirotaka Matsumoto

    Thank you for the reply. I would Try changing T2 to  1 ms for testing. 

    Please refer below table for the resistor ratios for different modes.

    Please request customer to review the resistor values for different modes. 

    Also can you please ask customer to review the RX_D2 and RX_D3 strapping resistor values and interchange the values as below.

    Regards,

    Sreenivasa

  • Hello Hirotaka Matsumoto

    Please request customer to first change the hardware and check before changing the T2 time.

    Regards,

    Sreenivasa

  • Hello Hirotaka Matsumoto-San, 

    Thank you for sharing the CN3 specifications.

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for your update.

    Please request customer to review the resistor values for different modes. 
    ->As we mentioned following thread, the customer checked the same contents with MODE1, MODE3 and MODE4. However, it occurs only MODE2. 
       e2e.ti.com/.../dp83867is-phy-address-setting-with-strap-pins 

    Also can you please ask customer to review the RX_D2 and RX_D3 strapping resistor values and interchange the values as below.
    ->The customer checked at RX_D2 and RX_D3 with MODE2, it occurs the same things. So, in case of MODE2, this problem occurs.


    Therefore, we assume that it is relation to device operates sampling at the device internally.
    Furthemore, we mentioned at the first of this thread;

    "Just before fixed of strap setting, it seems that pin's voltage raises.
     Why does the voltage raise? Because of SGMII interface, there is no packet.
     And these pins have only Mode2 resistor.
     Because of transition timing(from strap pin to clkout pin), does the voltage raise at the moment?"

    As our assumption, if this problem is rarecase to occur using only MODE2, we doubt that it has relation to the voltage raise at the moment just before fixed of strap setting.
    Could you let us know your opinion about it?

    Kind regards,

    Hirotaka Matsumoto

  • Hirotaka Matsumoto

    Thank you for the reply.

    Let me review.

    Please compare the strapping in the attached schematics with the strapping recommendations i shared in the previous thread. 

    Please ask customer to try changing the strap and check once.

    Regards,

    Sreenivasa

    .

  • Hello Hirotaka Matsumoto-San, 

    FYI, I put all the diagrams in the below thread.

    The strap value customer does not match any mode.

    Regards,

    Sreenivasa

  • Hello Hirotaka Matsumoto-San, 

    Please expect delay in response due to year end holidays.

    Regards,

    Sreenivasa

  • Kallikuppa san

    We are sorry that we makes your counfuse.
    未実装 means "Unpop" in Japanese.
    RX_D2 is Mode4.

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San,

    Thank you for the reply and No problem.

    Please read below note and let me know if you have any thoughts.

    For SGMII Mode 4 strap, TI recommends using Rhi = 4 kΩ and Rlo = 10 kΩ on RX_D0 and RX_D1 , RX_D2 and RX_D3.

    Regards,

    Sreenivasa

  • Kallicuppa san

    Thank you for your reply.

    Let me review.
    Please compare the strapping in the attached schematics with the strapping recommendations i shared in the previous thread. 
    Please ask customer to try changing the strap and check once.
    ->On RX_D2 pin, the customer already tested with MODE2 R485=R488=10kohm and R483=R486=2.49kohm, however it occurs the same trouble.
       Therefore, we assume that this problem is not concurned with pins.

    Kind regards,

    Hirotaka Matsumoto

  • Kallikuppa san

    For SGMII Mode 4 strap, TI recommends using Rhi = 4 kΩ and Rlo = 10 kΩ on RX_D0 and RX_D1 , RX_D2 and RX_D3.
    ->We would like to confirm above mention.
        The customer said they could set address setting with the Mode4 correctly Rhi = 2.49kΩ and Rlo = open (like as the datasheet description).
        "With SGMII Mode 4 strapTI recommends using Rhi = 4 kΩ and Rlo = 10 kΩ on RX_D0 and RX_D1 , RX_D2 and RX_D3,"
        does it affect for Mode2 also? We don't understand why we need to set Mode4 setting.
        We would like to know why the problem occurs with Mode2 only. With correct Mode4 setting, does Mode2 mis-reading problem resolve?

    Kind regards,

    Hirotaka Matsumoto 

  • And we are sorry that we mistaked to push "This resolved my issue botton".


  • Hello Hirotaka Matsumoto-San,

    Thank you.

    ->On RX_D2 pin, the customer already tested with MODE2 R485=R488=10kohm and R483=R486=2.49kohm, however it occurs the same trouble

    Ca you confirm with the same strap setting for RX_D0 and RX_D2, did customer change the straps for D1 and D3.

    Did customer observed error on D0 and not on D2 ?

    Regards,

    Sreenivasa

  • Hello Hirotaka Matsumoto-San,

    No problem. 

    Thank you for the reply. I do not know for sure if this will resolve the issue.

    A good practice is to resolve any other errors observed while testing. The strap of focus is the other address setting pin. 

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for your update.

    Can you confirm with the same strap setting for RX_D0 and RX_D2,
    ->Does it mean for example RX_D0=RX_D2=Mode2 or  RX_D0=RX_D2=Mode4?

    Did customer change the straps for D1 and D3?
    ->Does it mean "When operating in SGMII mode, dummy straps must be added to provide a balanced load for the SGMII differential pairs."? 
    Yes, in case of SGMII setting, of course, dummy straps must be added to provide a balanced load for the SGMII differential pairs. 

    Did customer observed error on D0 and not on D2 ?
    ->They confirmed it both pins with MODE2 only.
        In case of MODE1, 3, 4, there is no problem, however this problem occurs Mode2.

    Kind regards,

    Hirotaka Matsumoto

  • Kallikuppa san

    We are sorry that we would like to confirm one point increaseing T2 time from400us to 1ms.
    Does your T2 mean as following?(increasing between red two lines)?



    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San,

    Thank you for the reply. 

    ->Does it mean for example RX_D0=RX_D2=Mode2 or  RX_D0=RX_D2=Mode4?

    The issue is only observed with mode 2. So i would wan to check if customer tried setting same straps for D0 and D2. 

    This may not cause any issue but checking if D1 and D3 also was has straps similar to D0 and D2.

    ->They confirmed it both pins with MODE2 only.
        In case of MODE1, 3, 4, there is no problem, however this problem occurs Mode2.

    Does customer see the issue on D0 only or D0 and D2 in mode 2. I am not able to understand from the above note. Please elaborate.

    Regards,

    Sreenivasa

  • Hello Hirotaka Matsumoto-San,

    Thank you for the reply.

    Yes,  please increase the time and check if here is any improvement..

    Regards,

    Sreenivasa

  • Kallikuppa san

    The issue is only observed with mode 2.
    So I would wan to check if customer tried setting same straps for D0 and D2. 
    This may not cause any issue but checking if D1 and D3 also was has straps similar to D0 and D2.
    ->The customer tried setting same straps for D0 and D2.
       Then, about D1 and D3, they configured with the same constant corresponding for D0 and D2.
       Because the datasheet shows "dummy straps must be added to provide a balanced load for the SGMII differential pairs".
       Is it correct?

    Does customer see the issue on D0 only or D0 and D2 in mode 2. I am not able to understand from the above note. Please elaborate.
    ->They confirmed with D0 only, D2 only, and D0=D2 in mode 2 any cases.

    Kind regards,

    Hirotaka Matsumoto

  • Kallikuppa san

    Yes,  please increase the time and check if here is any improvement..
    -> OK, we will feed back you.

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San,

    Thank you for the reply.

    Does customer see the issue on D0 only or D0 and D2 in mode 2. I am not able to understand from the above note. Please elaborate.
    ->They confirmed with D0 only, D2 only, and D0=D2 in mode 2 any cases.

    Can i assume the the issue is found in both D0 and D2 in mode 2 ?

    Regards,

    Sreenivasa

  • Hello Hirotaka Matsumoto-San,

    Noted and thank you.

    Regards,

    Sreenivasa

  • Kallikuppa san

    Can i assume the the issue is found in both D0 and D2 in mode 2 ?
    ->Yes! So, we don't understand why the problem occurs only with 1 out of 400 in mode 2.
        Therefore, we asked you sampling time, transition timing(from strap pin to clkout pin), voltage raise at transition timing.
      

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San,

    Thank you for the reply. 

    Can you please ask customer to measure the 1.8V VDDIO and the ripple ?

    Hardware configuration latch-in time from the deassertion of RESET (either soft or hard) is 120ns.

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for the reply.
    Can you please ask customer to measure the 1.8V VDDIO and the ripple ?
    ->VDDA1P8=VDDIO, it seems that there is no big ripple.


    Hardware configuration latch-in time from the deassertion of RESET (either soft or hard) is 120ns.
    ->Of course, we know it on the datasheet.
       So, does the same voltage(static) need during 120ns?
       On the following waveform, pins voltage raise within 120ns after RESET=high.
       20211220_DP83867.pdf
       Does this raising voltage affect for hardware configuration sampling?

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San,

    Thank you for the query.

    Hardware configuration latch-in time from the deassertion of RESET (either soft or hard) is 120ns.
    ->Of course, we know it on the datasheet.

    Thank you for letting me know and noted.


       So, does the same voltage(static) need during 120ns?

    The range is provided to take care of the variation. The wave form which it occurs problem(mis-reading) doe not show the reading similar to the other waveform where no error occurs.

    I am assuming that the voltage is less when the failure is happening. Let me know your observations from the plot.

    Is the customer doing the SGMII interface before the RESET?

    Regard,

    Sreenivasa

  • Kallikuppa san

    Thank you for your update.

    I am assuming that the voltage is less when the failure is happening.
    ->Even though we confirm the wave forms between normal(OK) case and failure case(NG), it is not any voltage difference.
    20211220_DP83867.pdf
       That's why, we need your advice.

    Let me know your observations from the plot.
    ->Within 120ns, it seems that Hardware configuration latch-in time completed. Is it correct operation?
       When RX_D0 is low, does it mean that Hardware configuration finishes? Or, when the RX_D0's voltage raises, does Hardware configuration finishes?
       During RX_D0's voltage raising, does the device keeps sampling?


    Is the customer doing the SGMII interface before the RESET?
    ->Please let us know the background of this question. Before the RESET, if the setting is not SGMII, does it problem occur?
        As the customer's operation,
        1. start up with Figure2 timing sequence
        2. confirmation of address setting
        3. RESET_low
        4. RESET_High
        5. confirmation of address setting
        ...... Repeat of  from 3 to 5, this problem occurrs 1 out of 400 reoccurrence. 
        As the result, we assume that the MAC setting is SGMII before the RESET.

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San,

    Thank you for the reply.

    The waveforms for the normal and failed situation scaling is not same. 

    Regards,

    Sreenivasa

  • Hello Hirotaka Matsumoto-San,

    Let me know your observations from the plot.
    ->Within 120ns, it seems that Hardware configuration latch-in time completed. Is it correct operation?

    Yes this is correct. I do not se any minimum time specified in the datasheet.


       When RX_D0 is low, does it mean that Hardware configuration finishes?

    The RX_D0 and RX_D1 transition is indicating hardware configuration complete.

    Or, when the RX_D0's voltage raises, does Hardware configuration finishes?

    I assume this is the latching time.


       During RX_D0's voltage raising, does the device keeps sampling?

    I will have to check on the latching mechanism. 

    Regards,

    Sreenivasa

  • Is the customer doing the SGMII interface before the RESET?
    ->Please let us know the background of this question. Before the RESET, if the setting is not SGMII, does it problem occur?

    This is to confirm all the measurements are made with the MAC and PHY being in a known condition. The PHY is set to SGMII by straps and hence checking the MAC.


        As the customer's operation,
        1. start up with Figure2 timing sequence
        2. confirmation of address setting
        3. RESET_low
        4. RESET_High
        5. confirmation of address setting
        ...... Repeat of  from 3 to 5, this problem occurrs 1 out of 400 reoccurrence. 
        As the result, we assume that the MAC setting is SGMII before the RESET.

    Can you please check if the error is happening randomly in 400 iterations or in some known sequence.

     

    Regards,

    Sreenivasa

  • Kallikuppa san

    Thank you for your update.

    I will have to check on the latching mechanism. 
    ->OK, we are looking forward to your updat.

    Can you please check if the error is happening randomly in 400 iterations or in some known sequence?
    ->The error is happening randomly in 400 iterations. 
       Even though the voltage is the same between normal(OK) case and failure case(NG), the error(address mis-reading) occurs.
       Therefore, we asked you internal sampling timing.
       

    Kind regards,

    Hirotaka Matsumoto

  • Hello Hirotaka Matsumoto-San,

    Wishing you a happy new year 2022.

    Here are the inputs i received and let me know if this helps.

    We don’t explicitly define the  timing spec for strap latching. Customer shall maintain the voltage on pins for the whole 200 ns.

    These are sampled only once. Value in d/s is typical and not max. These are sampled through I/O which have both analog and digital logic.

    Can you ask customer to add a small filter cap on the VDDIO supply near to the strap for testing purpose.

    Regards,

    Sreenivasa