DP83620: MII bus idle

Hello Marc-André Filion

Thank you for the query.

Could you please share the PDF schematics. If you could provide the MAC and MDI  interface section of the schematics that would help.

Regard,

Sreenivasa

Hi,

I've create a PDF that is only showing the Ethernet portion of my schematic with sensitive information hidden.DP83620_Ethernet Schematic.pdf

Hope is help

Regards,

Marc-Andre

Hi Sreenivasa,

I've check if the PHY could be in MII isolate mode. All device MII output are firmly driven low. When I assert the power-down pins, the outputs are now Hi-Z.

Does the PHY wait for a MDIO transaction before activation? the MCU is not programmed yet. We just have a code that release the resets.

regards,

Marc-Andre

Hello Marc-André Filion

Thank you for the inputs.

Can you please check the PHY address. An address zero puts the device into MII isolate mode.

One cause could be the clock coming up after the ese is released. 

4.5 AC Specifications — Power Up Timing

Please make sure the clock is stable before the reset_n is released.

Regards,

Sreenivasa

Hello Marc-André Filion

If you are concerned on sharing sensitive information, you could use the private chat.

Regards,

Sreenivasa

The PHY Address is 1. I can see the high level on COL when the device is held in reset and it drop to 0 when reset is released.

Hello Marc-André Filion

Thanks. Can you please check the clock and reset sequence please.

Please allow the clock to stabilize before releasing the reset.

Regards,

Sreenivasa

Hello Marc-André Filion

How is the supply ramp time ? Can you try performing a RESET using Bit5 0f 10.1.1 Basic Mode Control Register (BMCR) after power up.

Regards,

Sreenivasa

Hi,

The supply ramp time is 10ms. It's monotonic. Unfortunately, we don't actually have SW hook to access the MDIO interface. We are working on that with our FW team.

We add a 1sec delay between power-on and reset released. I will take a closer look at the reset release vs clock later this afternoon.

Hi,

I've took snapshot of the reset vs clock. My probing is not optimal. That may lead to some over/undershoot that aren't actually there.

In some cases, the clock is undersampled. This lead to oscilloscope artifact.

I would like to know if there's any mode that could lead the PHY to tied all the output low. Could it be a factory test mode that is activated by mistake?

Channel 1: Clock 25MHz

Channel 2: Reset

Channel 3: 3.3V

Power-up sequence:

Clock vs reset released:

3.3V ramp-up vs clock (the 25MHz clock is undersampled):

Hello Marc-André Filion

The supply ramp should be fine. 

I will wait for your other test observations.

Regards,

Sreenivasa

Hi,

I would like to get know a few detail about this PHY behavior. 

Does the PHY MII port remain idle when there's no Ethernet link? Is the MII active when the Link is open?

If the MII is supposed to be always active. (minimally the clocks) Is there any operating modes that could lead the PHY to keep those lines tied low? Could it be a factory test mode, or a JTAG test mode?

Does the Reset input rise time could have an effect on the PHY behavior?

Thanks,

We manage to write to the PHY, but the reset don't seem to change anything. We will review the whole board assembly again to see if all the part and all the solder are ok. 

Hello Marc-André Filion

I expect the MII clock to be active if the MII isolate is not enabled by address 0.

Thanks,

Sreenivasa

Hello Marc-André Filion

Thank you for updating. Agree with your approach.

Regards,

Sreenivasa