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TLK10081: GbE link aggregation and CTC

Jose Garcia
Prodigy 10 points
Part Number: TLK10081

Hello sirs,

I'm planning to employ the TLK10081 for mux/demultiplexion or six Gigabit Ehternet channels in the same way as Application Report: SLLA347 but after reading througly the datasheet and the report I have some questions:

1. In SLLA347 the TLK10081 is configured in bit interleave mode. Does Clock Tolerance Compensation works with this configuration? (I understand it doestn't since the device can't aling to 10bit words in this mode)

2. The reference clock for both TLK10081 sides in SLLA347 block diagram  seems to be the same. Whould the TLK10081 configured in this manner work properly for this application providing the reference clock for the two devices are different and consequenly not in phase?

3. What are the GIGE mode bits on transmit and receive path (register 1x1C LS_CH_CONTROL: bits 8,9)?

4. Lastly, if you can provide more information or advice for the Gigabit Ethernet agregation application it will be very welcome.

Best regards,

Jose.

  • 0
    TI__Mastermind 20192 points

    Hi Jose,

    1) I believe it should be possible to use clock tolerance compensation while in bit interleave mode.

    2) This should be fine since the TLK10081 also recovers the clock from the high speed data.

    3) Due to the age of this part, we are not very familiar with it and our knowledge about the part is limited to the datasheet.  Because of this, we are not positive what these bits do, but we suspect you might want to enable them if transmitting gigabit ethernet (GIGE) through the device.

    4) I don't have much experience with this part due to its age, so because of this I don't have any meaningful advice that I can provide.  Please feel free to reach out with additional questions though and we will try to answer them.

    Thanks,

    Drew

  • 0 in reply to Drew Miller1
    Prodigy 10 points

    Hello Drew, thanks for the support

    The matter is the following:

    Is CTC necesary when ref-clocks for both sides are not in phase?

    I understand it is, since the tlk10081 have two diferent clock domains (high and low speed) and I don't see the way to make the device work with high-speed recovered clock in TX low speed side or viceversa.

    May be I'm wrong, but without the CTC capability the phase-correction FIFOs will under/overflow soon or later.

    In case CTC is neccesary I don't see possible to make it work for gigabit ethernet aggregation because the iddle /I2/ in Ethernet PCS specification is composed of two characters (20bits) and the CTC in TLK10081 works replaccing 10bit characters.

  • 0 in reply to Jose Garcia
    TI__Mastermind 20192 points

    Hi Jose,

    I will look into this and will get back to you.

    Thanks,

    Drew