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XIO2001: GRST# behavior

Vitor Blauth
Prodigy 20 points
Part Number: XIO2001

Dear Sirs,

Is there a way to know if internal reset is active in XIO2001? Can I read GRST# pin to know if internal reset is happening?

Thank you

  • 0
    TI__Guru 60865 points

    Hello Vitor,

    No, there is no internal status that can be read for the GRSTz pin because it resets all the registers to their defaults.

    When GRST is asserted low, all control registers, state machines, sticky register bits, and power management state machines are initialized to their default state. In addition, the bridge asserts PCI bus reset ( PRST). When the rising edge of GRST occurs, the bridge samples the state of all static control inputs and latches the information internally. If an external serial EEPROM is detected, then a download cycle is initiated. Also, the process to configure and initialize the PCI Express link is started. The bridge starts link training within 80 ms after GRST is deasserted.

    Regards,

    JMMN

  • 0 in reply to JMMN
    Prodigy 20 points

    Hello JMMN,

    Thank you for the answer. 

    Then I understand I can read PRST as an indirect way to detect GRST occurences, right?

  • +1 in reply to Vitor Blauth
    TI__Guru 60865 points

    Hi Vitor,

    Yes. that would work if you have the ability to check PRST.

    Regards,

    JMMN