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XIO2001EVM: XIO2001 not initialized

Part Number: XIO2001EVM
Other Parts Discussed in Thread: XIO2001

We are using an XIO2001EVM board on an NXP T1042RDB evaluation board (under a yocto linux) to check compatibility before to design our own hardware.

On XIO2001EVM board, we insert a PCI board on a PCI slot. 

lspci shows that XIO2001 and PCI board are correctly discovered.

0002:01:00.0 PCI bridge: Texas Instruments XIO2001 PCI Express-to-PCI Bridge (prog-if 00 [Normal d
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <P
        Latency: 0, Cache Line Size: 32 bytes
        Bus: primary=01, secondary=02, subordinate=02, sec-latency=0
        I/O behind bridge: 00001000-00001fff
        Memory behind bridge: e0000000-e04fffff
        Prefetchable memory behind bridge: 00000000fff00000-00000000000fffff
        Secondary status: 66MHz+ FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR-
        BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
        Capabilities: [40] Subsystem: Device 0000:0000
        Capabilities: [48] Power Management version 3
                Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
                Bridge: PM- B3+
        Capabilities: [50] MSI: Enable- Count=1/16 Maskable- 64bit+
                Address: 0000000000000000  Data: 0000
        Capabilities: [70] Express (v2) PCI-Express to PCI/PCI-X Bridge, MSI 00
                DevCap: MaxPayload 512 bytes, PhantFunc 0
                        ExtTag- AttnBtn- AttnInd- PwrInd- RBE+
                DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
                        RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- BrConfRtry-
                        MaxPayload 128 bytes, MaxReadReq 512 bytes
                DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
                LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <
                        ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp-
                LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
                        ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
                LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
                DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
                DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
                LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
                         Transmit Margin: Normal Operating Range, EnterModifiedCompliance- Complia
                         Compliance De-emphasis: -6dB
                LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase
                         EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
        Capabilities: [100 v1] Advanced Error Reporting
                UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- Un
                UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- Un
                UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- Un
                CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
                AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-

0002:02:06.0 Communication controller: ILC Data Device Corp Device 1e00 (rev ba)
        Subsystem: ILC Data Device Corp Device 1e00
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2
        Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR-
        Latency: 128, Cache Line Size: 32 bytes
        Interrupt: pin A routed to IRQ 17
        Region 0: Memory at c20000000 (32-bit, non-prefetchable) [size=512]
        Region 1: I/O ports at 1000 [size=256]
        Region 2: Memory at c20200000 (32-bit, non-prefetchable) [size=2M]
        Region 3: Memory at c20400000 (32-bit, non-prefetchable) [size=16K]
        Capabilities: [40] Power Management version 2
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
        Capabilities: [48] CompactPCI hot-swap <?>
        Capabilities: [4c] Vital Product Data
                Unknown large resource type 5c, will not decode more.


When we test the PCI board, no interrupt are detected (an interrupt is allocated on the driver but no interrupt occurs)?

It seems that we have to modify the linux device tree to link/allocate an interrupt.

A pcie bus is defined like that :

 pcie@ffe260000 {
  compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
  reg = <0xf 0xfe260000 0x0 0x1000>;   /* registers */
  law_trgt_if = <2>;
  #address-cells = <3>;
  #size-cells = <2>;
  device_type = "pci";
  bus-range = <0x0 0xff>;
  ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
     0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */

What should we do to add to declare xio2001 with an interrupt.  


  • Hi Eric,

    Linux driver or environment has not been validated with XIO2001 device and it is not supported. This part was developed some time back and at that time this was not a requirement.


  • Hi Nasser,

    I think XIO2001 device is a bridge like all other transparent bridges... No need to have a specific driver for it: As you can see, the devices on PCI bus are enumerated successfully and we can access to theses devices without any problem.

    However, when the bridge receives  an interrupt on PCI bus, nothing is performed because they are not defined. I think, we need only to specify these interrupt on the device tree.

    My only issue is how do I describe the XIO2001 in a device tree for this interrupt to be initialized.


  • Hi Eric,

    Device was not tested in this environment.

    There is EEPROM settings that defines different configuration settings. I have attached copy of this and hope this helps.


  • Hi Nasser,

    This configuration should not help us.  

    In an Intel environnement, the BIOS performs the initialisation of the chip (as a standard PCI bridge): an interrupt is assign to the chip. Without BIOS, this initialisation should be done by defining a device tree.

    I think, you use these device tree on your processor plateform using a Linux OS for example.

    My problem is how to add the XIO2001 in the device tree.

    Please, tell me where i can have an answer ?