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TLK10031: Lane alignment is not achieved on the LS side

zhang jingbin
Prodigy 50 points
Part Number: TLK10031
Other Parts Discussed in Thread: TLK10232

 TLK10031_LS.pdf

our system is as attachment pdf. our TLK10031 config is as follows:

global reset"

"0x8610" > "0x401E0000"

#disable auto-negotiation

"0x2000" >"0x40070000"

#turn off lt_training

"0x0" > "0x401E0096"

#link setting configured manually

"0x03FF" > "0x401E8020“


#HS_SERDES_CONTROL_2

"0x4848" > "0x401E0003"


#HS_SERDES_CONTROL_3
"0xD500" > "0x401E0004"

#data path reset
"0x0008"  > "0x401E000E"

frist seconds ,  CHANNEL_STATUS_1 is 0x1c03 , the but, after a while，the register CHANNEL_STATUS_1 is changed to 0x5c03 .which means Lane alignment is not achieved on the LS side

can you give me the reason for it ？？ thanks

  • 0
    TI__Mastermind 20192 points

    Hi,

    What sort of data are you transmitting?  Is the data leaving the SERDES PHY 8b/10b encoded?  In order to achieve lane alignment, it's important to ensure that sufficient alignment characters are being received by the LS side of the TLK10031.

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    Prodigy 50 points

    Hi 

      the sort data is K28.5 from PCS , and the data is 8B/10B encodered.  In the first seconds, the  CHANNEL_STATUS_1  is 0x1c03 , it has been align successed。But why it is down after a while？ 

  • 0 in reply to Drew Miller1
    Prodigy 50 points

    Hi

    CHANNEL_STATUS_1  is 0x1c03 ，the bit [2] TX_LS_OK =0 means  not link on TL10031 LS side

    the bit [3] and the bit [14] are 0 which means  receive LS side align and link status 

    If the TL10031 LS SIDE and external serdes PHY are ok, it means CHANNEL_STATUS_1  = 0x1c0f . is it right?

    How to fix the problem? thanks

  • 0 in reply to Drew Miller1
    Prodigy 50 points

    Hi

    the register LS_LN0_ERROR_COUNTER---LS_LN3_ERROR_COUNTER are all zero . 

  • 0 in reply to Drew Miller1
    Prodigy 50 points

    HI 

    I am Confused with the value of the register channel_status_1 .

    in the pdf "Bring Up Procedures.pdf"

    i find 10G-KR with manual mode settings （connectting to SFP+）, the correct value for channel_status_1  is 0x5c03

    so can you tell me why ?

  • 0 in reply to zhang jingbin
    TI__Mastermind 20192 points

    Hi,

    Apologies for the confusion.  I think that this is an error in the datasheet.  The TLK10232 is an almost identical part.  I have confirmed in the TLK10232 datasheet and register map that LS_ALIGN_STATUS = 1 actually indicates that lane alignment has been achieved on the LS side.

    Are you running into additional issues in bringing up the link?

    Thanks,
    Drew

  • 0 in reply to Drew Miller1
    Prodigy 50 points

    Hi drew

    thanks for your reply

    We have an another problem which is described in the attached PDF

    7635.TLK10031_LS.pdf

     tlk10031 connects to switch through SFP+ , the upper block MAC are sometimes detect remote fault （sequence）which means switch mac has a local fault . How to find whether if tlk10031 tx parameters are ok?? how to optimize the TX parameters？？

    for tlk10031 receive， it always link up and the register channel_status_1 is also 0x5c03 . it seems the tlk10031 receiver works well. 

  • 0 in reply to zhang jingbin
    TI__Mastermind 20192 points

    Hi,

    Are you able to measure the eye diagram at the SFP+ port?  You can use SFF 8431 to see the eye mask requirements for an SFP+ module.

    In terms of adjusting TX parameters, you are able to adjust the pre-cursor, post-cursor, and swing of the TX signal.

    Thanks,
    Drew