TLK10031: Lane alignment is not achieved on the LS side

Hi,

What sort of data are you transmitting?  Is the data leaving the SERDES PHY 8b/10b encoded?  In order to achieve lane alignment, it's important to ensure that sufficient alignment characters are being received by the LS side of the TLK10031.

Thanks,
Drew

Hi 

  the sort data is K28.5 from PCS , and the data is 8B/10B encodered.  In the first seconds, the  CHANNEL_STATUS_1  is 0x1c03 , it has been align successed。But why it is down after a while？ 

Hi

CHANNEL_STATUS_1  is 0x1c03 ，the bit [2] TX_LS_OK =0 means  not link on TL10031 LS side

the bit [3] and the bit [14] are 0 which means  receive LS side align and link status 

If the TL10031 LS SIDE and external serdes PHY are ok, it means CHANNEL_STATUS_1  = 0x1c0f . is it right?

How to fix the problem? thanks

Hi

the register LS_LN0_ERROR_COUNTER---LS_LN3_ERROR_COUNTER are all zero . 

HI 

I am Confused with the value of the register channel_status_1 .

in the pdf "Bring Up Procedures.pdf"

i find 10G-KR with manual mode settings （connectting to SFP+）, the correct value for channel_status_1  is 0x5c03

so can you tell me why ?

Hi drew

thanks for your reply

We have an another problem which is described in the attached PDF

7635.TLK10031_LS.pdf

 tlk10031 connects to switch through SFP+ , the upper block MAC are sometimes detect remote fault （sequence）which means switch mac has a local fault . How to find whether if tlk10031 tx parameters are ok?? how to optimize the TX parameters？？

for tlk10031 receive， it always link up and the register channel_status_1 is also 0x5c03 . it seems the tlk10031 receiver works well.