SN75LVDS83B: what's the status of clock output when VDD is applied?

Hi Rayna,

When customer applies VDD, are they powering all power supply pins at once (i.e, VCC, IOVCC, PLLVCC, and LVDSVCC)? What is the status of the SHTDN pin when VDD is powered on?

Regards,

Jack

Hi Rayna,

As a quick follow up, is this behavior interfering with any other device or system?

Regards,

Jack

Hi Jack,

yes, they power all supplies when VDD is applied. SHTDN is always connect to VDD as SCH showed. Are you suspecting this is affected by other devices?  I'd like to know for SN75LVDS83, when SHTDN is pull-up, what's the status of its LVDSCLK output? Is it internally pull up or pull down, or tri-state?

Regards,

Rayna

Hi Rayna,

Ruixin Feng said:

Are you suspecting this is affected by other devices?

Is the CLKOUT swing causing any effects on downstream devices (DES, display)?

Ruixin Feng said:

what's the status of its LVDSCLK output? Is it internally pull up or pull down, or tri-state?

All that is known is that LVDSCLK output is high-impedance when SHTDN is low. Given the age of this device, I cannot find much information beyond the datasheet.

Would you be able to attach the schematic for the SN75LVDS83B?

Regards,

Jack

Hi Jack,

I attached the sch for your reference. 

You want to confirm if CLKOUT swing affect downstream devices or CLKOUT swing is caused by downstream devices? 

Thx~

Rayna

Hi Rayna,

Thank you for the schematic.

I want to confirm if the CLKOUT swing is affecting downstream devices. Is this causing issues for the customer?

Regards,

Jack

No, but customer need to know the reason why it swings. According to datasheet, it should keep low-level voltage before CLK applied. Could you pls help to confirm its internal structure?

Rayna