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XIO2001: Period between writing SRST bit and changing PRST pin.

Motoyasu Hattori
Genius 9065 points
Part Number: XIO2001

Hi,

My customer has two following questions of XIO2001 RESET on secondary bus.

  1. When they writes 0 on SRST bit of "Bridge Control Register", XIO2001 asserts Low on PRST pin ASAP, regardless of PCI status (ex. during transferring data).  If they wants to de-assert HIGH on PRST pin, they writes 1 on SRST bit ASAP.  Is my understand correct?
  2. If yes, how much time does it take from writing 0 to asserting PRST pin?   Also, does this timing synchronize with PCI Clock?   Please advise us.

Thanks and best regards,
M.HATTORI.

  • 0
    TI__Mastermind 20870 points

    Hi M.Hattori,

    1.  Setting the SRST bit to 1 asserts PRST#, which means it will be low since it is an active low signal.  If the value is 0, it will be de-asserted or high.  
    "Secondary bus reset. This bit is set when software wishes to reset all devices downstream of the bridge. Setting this bit causes the PRST signal on the secondary interface to be asserted.
    0 = Secondary interface is not in reset state (default)
    1 = Secondary interface is in the reset state"  - XIO2001 Datasheet, Section 8.4.30

    2. The PRST signal is asynchronous to the PCI bus clock.  Section 6.9 shows that the input transition time is 1 to 4 nanoseconds, so it could be similar, but I don't see any information about output transition time.
    "PRST is a required PCI bus signal and must be connected to all devices. This output signal is asynchronous to the PCI bus clock. Since the output driver is always enabled and either driving high or low, no pullup resistor is needed."     - XIO2001 Datasheet, Section 9.2.1.2.1
    The 

    Regards,

    Nicholaus