Hi Expert,
My customer using TPD1E01B04-Q1 as the ESD protection for FPD-LINK
From customer perspective, on the ESD protection of the high-speed interface, the parasitic capacitance will affect the TDR.
If it is convenient for you, would you mind sharing some technical application notes of ESD Anti pad?
Thanks a lot for your warm help!
Hi Sebastian,
Thanks a lot for your warm help！
Here are other ESD suppliers
provide the curve of ESD influence of Mark4 TDR. Do we have such technical documents?
Hi Imelda.
We don't have any such technical documents using a TDR. For signal integrity purposes we conduct an insertion loss test with our low cap. diodes. The insertion loss graph shows the energy that a signal loses as the signal frequency on the input increases. Devices with higher capacitance will cause a higher insertion loss.
The general rule of thumb is to only protect signals with speeds below the -3dB point on the insertion loss graph.
Also TDR measurements will be affected by the PCB layout which will be different from customer to customer. If we conducted TDR measurements on a board with different trace sizes or different stackups, the results might not be easily replicated on the customer PCB.
Regards,
Sebastian
