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DP83826I: FPGA control DP83826 issue

Jason Cao
Prodigy 140 points
Part Number: DP83826I

FPGA connects two 100M PHY chips DP83826I and wants the chips to work in RMII SLAVE mode. FPGA provides two 50MHZ clocks to DP83826I.

Current phenomenon: FPGA controls two 83826 to send and receive data to each other for testing. The transmission is based on RMII’s 50MHZ, 2-bit rate, and the received data has only a speed of 25MHZ. The length of RX_DV and TX_EN is the same, and the 2-bit data send and receive comparison aside from the mismatch between 50M and 25M speed is sometimes wrong.

Register configuration order:

0x001f, 0x8000 //reset register, hard reset, wait for one second

0x0017, 0x0183 //RMII register, reference clock selection 50MHZ, rmii tx clock shift enable

0x0468, 0x109f //extended register, set RMII slave mode

0x001f, 0x4000 //reset register, soft reset, retain register configuration, reset hardware

  • 0
    TI__Genius 14005 points

    Hi Jason,

    How do you know the received data only has a speed of 25 MHz?

    When you say that the FPGA provides two clocks to DP83826I, does each DP83826I have one oscillator connected to XI only? Does the built in oscillator meet specs (±50 ppm-tolerance CMOS-level oscillator clock.)?

    Is pin 19 (RX_CLK/ 50MHz_RMII) pulled down?

    Best regards,

    Melissa

  • 0 in reply to Melissa Chang
    TI__Prodigy 140 points 
    Both the FPGA logic analyzer function and the oscilloscope can see the data transition pulse width.
    No oscillator, directly use CMOS3.3V clock.
    PIN19 is not pulled low, it is connected to the FPGA input pin, and it is in a high-impedance state.
     
  • 0 in reply to Jason Cao
    TI__Genius 14005 points

    Hi Jason,

    What is the topology of your system? Are the PHYs connected to one another in any way or are they connected to the FPGA separately?

    Were you able to get the ppm specs of the built in oscillator?

    Are you configuring both PHYs' registers?

    Best regards,

    Melissa

  • 0 in reply to Melissa Chang
    TI__Prodigy 140 points 
    Two phys are directly connected to an FPGA.
The two phys are two ways of mdio to configure the same register at the same time. The clock source is a 100m crystal oscillator that passes through the pll clock module inside the FPGA and outputs 50m to the two phys through the buffer. There is no ppm instrument data, but because it is not digitally synthesized, ppm should not be bad.
  • 0 in reply to Jason Cao
    TI__Genius 14005 points

    Hi Jason,

    Jason Cao said:
    he two phys are two ways of mdio to configure the same register at the same time.

    Are you saying that their MDIO/MDC lines are connected together? If so, are the addresses of the PHY configured to be different?

    Jason Cao said:
    ppm should not be bad.

    The +-50 ppm tolerance is important. Is there anyway you could find out what it is?

    How are you probing the data going out/in?

    Are you able provide registers 0x00-0x1E, 0x467, and 0x468  for both PHYs when data is being sent/received from the FPGA?

    Best regards,

    Melissa