DP83867E: DP83867ERGZT

HI Vidhya,

May I ask why did you need to know this information? In two power supply, there is an internal LDO to support VDDA1P8.

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Regards,

Hillman Lin

HI Hilman Lin,

Datasheet doesn't specify details about internal LDO. when pins are probed 1.8V is observed on those lines. 

There is an issue on board. Ethernet Ping works, but Port status is shown down in Control panel -->network in PC.

Link status and speed LED indications of RJ45 are off too.

Is this an expected behavior?   

Thanks and Regards,

Vidhya

Hi Vidhya,

We will discuss this with the team and get back to you later this week.

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Regards,

Hillman Lin

Ok. 

Also, Can you share oscilloscope capture reference for SGMII- TX, RX lines and MDI differential lines? To check the behavior in my setup?

Thanks,

Vidhya

Hi Vidhya,

May I ask you couple question for further debug?

• Are you able to read the register on the PHY? If so, could you read register 0x0000 to 0x01E and register 0x06E.
• Could you also check the power up sequence of the PHY? We want to make sure VDDA1P8 supply must be stable within 25ms of the VDDA2P5 supply ramping up.
• The register and link status of the register should give us a basic status of SGMII and MDI lines. Let check this before we move on to the oscilloscope.

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Regards,

Hillman Lin

Hi Hillman Lin,

There is no requirement for the sequence of the supplies when operating in two-supply mode. Does 25ms still be considered? VDDA1P8 is no connect in design.

I am facing issue on board. Not seeing output on MDI Lines and not able to access registers.

But am able to record PHY clock in and clock out 25MHz, SGMII Tx_P and N lines, Chip is out of reset, no interrupt too, Seeing MDC and MDIO lines are high.

Not sure if chip is damaged. Kindly share your thoughts.

Regards,

Vidhya

Hi Vidhya,

I will review it internally and get back to you early next week.

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Regards,

Hillman Lin

Hi Vidhya,

• In two power supply mode, the 25ms is taken care of internally within the chip with the internal LDO.
• Did you check the VDDA, VDDIO, and VDD2P5 voltage. Could you also check the Rbias voltage?
• When you said MDC is High, are you saying that the PHY is not generating the MDC clock signal.

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Regards,

Hillman Lin

HI Hillman Lin,

My comments are as follows.

1. Checked the delay between VDDA1P8 and VDDA2P5V which is 177ms

2. VDDA, VDDIO and VDD2P5 Voltages are fine.

Rbias pin voltage is measured to be 0V

3. I meant MDC is at 6MHz and is interfaced with FPGA.

Thanks and Regards,

Vidhya

Hi Vidhya,

I work on the same team as Hillman, and will be assist on this thread while he is OoO for a little bit. Could you please consult our app note on DP83867 troubleshooting, and run through the checks listed in this document? 

Sincerely,

Gerome