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DS90UB662-Q1: How DS90UB662-Q1 and DS90UB633-Q1 achieve data transfer

Part Number: DS90UB662-Q1

Hi Team,

Could you share a basic register configure for DS90UB662-Q1 to achieve video transfer function? Currently, customer configure as attached file shows, but they still can't achieve the video transfer from 633 to 662, could you please kindly help to check if we have something missing from software side? Thanks a lot for your support.

TI662 + 633.txt
TI 662:
0x4C,0x01, //RX Port0 write enable
0x58,0x58, //I2C pass-through, BCC 2.5Mbps
0x07,0xFF,   // disable  BCC  watchdog
0x09,0x81,
0x5C,0xb0, //633 address
//0x5D,0x06, //camera address
//0x65,0xB2, //camera address

0x4C,0x12, //RX Port1 write enable
0x58,0x58, //I2C pass-through, BCC 2.5Mbps
0x07,0xFF,   // disable  BCC  watchdog
0x09,0x81,
0x5C,0xb0, //633 address
//0x5D,0x06, //camera address
//0x65,0xB2, //camera address

0x4C,0x24, //RX Port2 write enable
0x58,0x58, //I2C pass-through, BCC 2.5Mbps
0x07,0xFF,   // disable  BCC  watchdog
0x09,0x81,
0x5C,0xb0, //633 address
//0x5D,0x06, //camera address
//0x65,0xB2, //camera address

0x4C,0x38, //RX Port3 write enable
0x58,0x58, //I2C pass-through, BCC 2.5Mbps
0x07,0xFF,   // disable  BCC  watchdog
0x09,0x81,
0x5C,0xb0, //   633 address
//0x5D,0x06, //camera address
//0x65,0xB2, //camera address

# "*** RX0 VC=0 ***"
0x4C,0x01 # RX0
0x70,0x1E # RAW10_datatype_yuv422 8bit_VC0
0X7C, 0xA0  //  8-bit processing using upper 8 bits
# "*** RX1 VC=1 ***"
0x4C,0x12 # RX1
0x70,0x5E # RAW10_datatype_yuv422 8bit_VC1
0X7C, 0xA0  //  8-bit processing using upper 8 bits
# "*** RX2 VC=2 ***"
0x4C,0x24   # RX2
0x70,0x9E # RAW10_datatype_yuv422 8bit_VC2
0X7C, 0xA0  //  8-bit processing using upper 8 bits
# "*** RX3 VC=3 ***"
0x4C,0x38    # RX3
0x70,0xDE    # RAW10_datatype_yuv422 8bit_VC3
0X7C, 0xA0  //  8-bit processing using upper 8 bits
# "CSI_PORT_SEL"
0x32,0x01   # CSI0 select
# "CSI_EN"
0x33,0x1    # CSI_EN & CSI0 4L
# "***Basic_FWD"
0x21,0x14     # Synchronized Basic_FWD
# "***FWD_PORT all RX to CSI0"
0x20,0x00      # forwarding of all RX to CSI0

//frame sync settings, For 2.5-Mbps backchannel operation,
//the frame period is 11200 ns (28 bits x 400 ns/bit).
//25fps
WriteI2C(0x4C,0x01) # RX0
WriteI2C(0x6E,0xAA) # BC_GPIO_CTL0: FrameSync signal to GPIO0/1
WriteI2C(0x4C,0x12) # RX1
WriteI2C(0x6E,0xAA) # BC_GPIO_CTL0: FrameSync signal to GPIO0/1
WriteI2C(0x4C,0x24) # RX2
WriteI2C(0x6E,0xAA) # BC_GPIO_CTL0: FrameSync signal to GPIO0/1
WriteI2C(0x4C,0x38) # RX3
WriteI2C(0x6E,0xAA) # BC_GPIO_CTL0: FrameSync signal to GPIO0/1
WriteI2C(0x10,0x91) # FrameSync signal; Device Status; Enabled
0x19,0x02,//FS_HIGH_TIME_1
0x1A,0xCA,//FS_HIGH_TIME_0
0x1B,0x19,//FS_LOW_TIME_1
0x1C,0x1C,//FS_LOW_TIME_0   
0x18,0x01,//FrameSync Enable

TI 633:
0x0D, 0x99   GPIO0/1 output enable

Best regards

Jie