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DS90UB948-Q1: how to calculation and select back channel 5Mbps or 20Mbps speed

HB ZHANG
Prodigy 50 points
Part Number: DS90UB948-Q1

Hello, team

        We use 948 as the deserializer for the car's IVI display; When we touch the IVI screen, the turetouch IC data will be uploaded to the MCU through the IIC signal, and then the data will be filtered and transmitted back to the SOC of the host through 948-947; When we set the Mode_ SEL1 is set to 20Mbps/STP, it is found that some touch data between MCU and 948 will be lost; When the mode_sel1 set to 5Mbps/STP,  it will not occur;
My question is:
1. How to calculate and select this 5Mbps or 20Mbps speed change to ensure it does not affect my current design?
2. Is there any other impact of back channel rate change, such as the video signals of forward channel ?

thanks!

  • 0
    TI__Guru** 100895 points

    Hello HB,

    In order to make sure that both the forward channel and back channel links are working correctly, you will need to ensure that the channel performance between SER/DES has strong insertion loss and return loss performance across the operating frequency range of both the forward and back channels. Also one of the common causes of issues in the back channel specifically is due to incorrect passive/component selection for the FPD-Link channel for example the AC coupling caps or CMC in the line. So if you want to share your schematics for this design we could help to review that. Both 5Mbps and 20Mbps are expected to operate error free, so I suspect that there is some design marginality here which is causing the poor performance at the higher speed. 

    As for the second question, the back channel speed does not have any impact on the forward channel video signals 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Prodigy 50 points

    Hello，Casey

               thanks for your feedback, the attachment is latest schematic for 948 module. maybe you can help double check our design. inaddition, we have margin analyse test for 947-948 channel; and the results is perfect, i am not sure that is reflect your said "insertion loss and return loss".

              Expect for your reply!

    3036.pdf

  • 0 in reply to HB ZHANG
    TI__Guru** 100895 points

    Hello HB,

    The result shown in MAP is an analysis of the forward channel signal only. The MAP tool does not have any way to analyze back channel performance. The best tool we have for back channel BER analysis is BIST which is described in the product datasheets. If there is an issue here with the back channel, that would be related to the channel performance specifically at the lower frequency range between ~1-20MHz. 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Guru** 100895 points

    HB,

    From the schematic what component is being used for the CMC?

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Prodigy 50 points

    Hello，Casey

            Do you want know that FPD-LINK channel common choke type? L3210/L3211 both are DLW21SZ900HQ2(Murata);

           we will to do test for BIST mode, and will feedback for you if has new found. now we more like to know that the how to selected back channel speed, and how to calculation?

           thank you!

  • 0 in reply to Casey McCrea
    Prodigy 50 points

    Hello, Casey

            The pass pin always high level during BIST mode ,we not found any question in BIST MODE.

    thanks!

  • 0 in reply to HB ZHANG
    TI__Guru** 100895 points

    Hello HB,

    The PASS pin on the DES is only monitoring forward channel errors, not back channel. In order to check the number of back channel errors, you must read register 0x1B on the 947 after the BIST test is disabled. Can you please check if you are getting back channel CRC errors during BIST?

    Besy Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Guru** 100895 points

    HB,

    As far as your question on how to select back channel speed, it is simply just based on your application needs. Higher back channel speed will allow for faster back channel GPIO speeds and slightly faster I2C round trip delay for access across the control channel. Also it can allow for higher back channel SPI speed if your application uses SPI. Those are the main factors which are influenced by back channel speed. 

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Prodigy 50 points

    Hello, Casey

          thanks for your remind, i will try it.