Dear team,
Customer uses the DP83867E and they I use, as a backup, its CLK_OUT output as input to an external PLL. They would like to reproduce this mechanism on other projects.
The idea is to use the PHY to extract the clock from the downstream system over synchronous Ethernet (they switch the CLK_O_SEL to 00000: Channel A receive clock).
It works until they disconnect the cable. When the cable is disconnected, they still have a clock on CLK_OUT but which drifts as the internal PLL is in holdover.
How can we extract the PLL holdover information from the PHY?
As much as if the cable is disconnected, it's quite easy to say that they can no longer trust their upstream clock, but that seems limited to them for other cases of failure, they would really like to check the level of confidence that they can have in this CLK_OUT output: does it come from a locked PLL, or simply the image of the XI input or from a PLL in holdover?
Thanks in advance for your reply.
Regards,
Pol.
