Dear Texas Instruments Design Engineering Team,
I have been communicating with your support team regarding the DP83867ISRGZ Ethernet PHY IC, specifically the ability to output a 125MHz clock from CLK_OUT regardless of the communication speed.
Through discussions with the support team and reviewing related forum posts, I have attempted to adjust the IO_MUX_CFG register, but the correct register settings to achieve my needs are still unclear.
Specifically, I want to configure the DP83867ISRGZ to continuously output a 125MHz clock on the CLK_OUT pin regardless of whether the communication speed is 10M, 100M, or 1000M.
I understand that the DP83867ISRGZ has a robust clocking feature set, and I am hoping to use your expertise to understand the appropriate settings for this particular use case.
I am requesting your assistance to provide in-depth insight and guidance on this matter. Any sample code or references to specific parts of the datasheet that could assist me would be greatly appreciated.
Thank you in advance for your time and expertise.
Best regards,
Hiroshi Sakurai
EBRAINS, Inc.
