DS99R105:DS99R105-6 / 波形品質

Hi Kotaro,

kotaro.nishimura said:

A clock component can be seen in the communication path every 125 ns,

Is the DS99R106 working with this clock component?

When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin. The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high, data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. So when you have any type of CLK disruption that will cause the Des not to lock to correct CLK frequency. 

kotaro.nishimura said:

If question 1 is correct, then if this clock is disturbed

Is it correct to assume that the DS99R106 side cannot receive the signal? 

Also, is it unacceptable if even one clock is disturbed?

Yes correct. 

kotaro.nishimura said:

Could you please provide a reference circuit diagram for DS99R105 and DS99R106 , which are resistant to noise ?

For reference design please refer to Eval kit document attached.

EVAL Kit DS99R105-106.pdf

Regards,
Fadi A.